Abstract
This chapter describes how to accomplish hierarchy within Verilog using lower-level subsystems. Structural design in Verilog refers to including lower-level subsystems within a higher-level module in order to produce the desired functionality. This is called hierarchy and is a good design practice because it enables design partitioning. A purely structural design will not contain any behavioral constructs in the module such as signal assignments, but instead just contain the instantiation and interconnections of other subsystems. A subsystem in Verilog is simply another module that is called by a higher-level module. Each lower-level module that is called is executed concurrently by the calling module.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
LaMeres, B.J. (2019). Structural Design and Hierarchy. In: Quick Start Guide to Verilog. Springer, Cham. https://doi.org/10.1007/978-3-030-10552-5_4
Download citation
DOI: https://doi.org/10.1007/978-3-030-10552-5_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-10551-8
Online ISBN: 978-3-030-10552-5
eBook Packages: EngineeringEngineering (R0)