Machine Learning in VLSI Computer-Aided Design pp 323-348 | Cite as

# Fast Statistical Analysis Using Machine Learning

## Abstract

In this chapter, we describe a fast statistical yield analysis methodology for memory design. At the heart of its engine is a mixture importance sampling-based methodology which comprises a uniform sampling stage and an importance sampling stage. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance sample points simulations. To avoid overfitting, we rely on a cross-validation-based regularization framework for ordered feature selection. The methodology is comprehensive and computationally efficient. We demonstrate the methodology on an industrial state-of-the-art 14 nm FinFET SRAM design with write-assist circuitry. The results corroborate well with hardware and with the fully circuit-simulation-based approach.

## Notes

### Acknowledgements

The authors would like to thank the Maroun Semaan Faculty of Engineering and Architecture at the American University of Beirut for supporting Ph.D. student Miss Lama Shaer.

## References

- 1.X. Li, H. Liu, Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations, in
*Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE*(IEEE, New York, 2008), pp. 38–43Google Scholar - 2.K. Agarwal, S, Nassif, Statistical analysis of SRAM cell stability, in
*Proceedings of the 43rd annual Design Automation Conference*(ACM, New York, 2006), pp. 57–62Google Scholar - 3.S. Mukhopadhyay, H. Mahmoodi, K. Roy, Statistical design and optimization of SRAM cell for yield enhancement, in
*Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design*(IEEE Computer Society, Washington, DC, 2004), pp. 10–13Google Scholar - 4.A. Singhee, R.A. Rutenbar, Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application, in
*Design, Automation, and Test in Europe*(Springer, New York, 2008), pp. 235–251Google Scholar - 5.R. Kanj, R. Joshi, S. Nassif, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events, in
*Design Automation Conference, 2006 43rd ACM/IEEE*(IEEE, New York, 2006), pp. 69–72Google Scholar - 6.R. Kanj, T. Li, R. Joshi, K. Agarwal, A. Sadigh, D. Winston, S. Nassif, Accelerated statistical simulation via on-demand Hermite spline interpolations, in
*Proceedings of the International Conference on Computer-Aided Design*(IEEE Press, New York, 2011), pp. 353–360Google Scholar - 7.M. Malik, R.V. Joshi, R. Kanj, S. Sun, H. Homayoun, T. Li, Sparse regression driven mixture importance sampling for memory design, in
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*(2017)Google Scholar - 8.L. Shaer, R. Kanj, R. Joshi, M. Malik, A. Chehab, Regularized logistic regression for fast importance sampling based SRAM yield analysis, in
*2017 18th International Symposium on Quality Electronic Design (ISQED)*(IEEE, New York, 2017), pp. 119–124Google Scholar - 9.G.E.P. Box, J. Stuart Hunter, W. Gordon Hunter,
*Statistics for Experimenters: Design, Innovation, and Discovery*, vol. 2 (Wiley, New York, 2005)zbMATHGoogle Scholar - 10.J.F. Ramaley, Buffon’s noodle problem. Am. Math. Mon.
**76**(8), 916–918 (1969)MathSciNetCrossRefGoogle Scholar - 11.N. Metropolis, S. Ulam, The Monte Carlo method. J. Am. Stat. Assoc.
**44**(247), 335–341 (1949)CrossRefGoogle Scholar - 12.C.P. Robert.
*Monte Carlo Methods*(Wiley Online Library, 2004)Google Scholar - 13.T.C. Hesterberg, Advances in importance sampling, PhD Thesis, 1988Google Scholar
- 14.D.W Hosmer Jr., S. Lemeshow, R.X. Sturdivant,
*Applied Logistic Regression*, vol. 398 (Wiley, New York, 2013)Google Scholar - 15.A. Mojsilovic, A logistic regression model for small sample classification problems with hidden variables and non-linear relationships: an application in business analytics, in
*IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005. Proceedings (ICASSP’05)*, vol. 5 (IEEE, New York, 2005), pp. v–329Google Scholar - 16.S. Ahmad, N.M. Ramli, H. Midi, Outlier detection in logistic regression and its application in medical data analysis, in
*2012 IEEE Colloquium on Humanities, Science and Engineering (CHUSER)*(IEEE, New York, 2012), pp. 503–507Google Scholar - 17.R.S. Collica, A logistic regression yield model for SRAM bit fail patterns, in
*The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993*(IEEE, New York, 1993), pp. 127–135Google Scholar - 18.X. Li, H. Liu, Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations, in
*Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE*(IEEE, New York, 2008), pp. 38–43Google Scholar - 19.A. Ng, Cs229 lecture notes (2017). Retrieved from http://cs229.stanford.edu/notes/cs229-notes-all/
- 20.X. Li, Finding deterministic solution from underdetermined equation: large-scale performance variability modeling of analog/RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
**29**(11), 1661–1668 (2010)CrossRefGoogle Scholar - 21.D. Böhning, Multinomial logistic regression algorithm. Ann. Inst. Stat. Math.
**44**(1), 197–200 (1992)CrossRefGoogle Scholar - 22.D.T, Larose,
*Data Mining Methods & Models*(Wiley, New York, 2006)Google Scholar - 23.T.P. Minka, A comparison of numerical optimizers for logistic regression, Unpublished draft (2003)Google Scholar
- 24.S.-I. Lee, H. Lee, P. Abbeel, A.Y. Ng, Efficient L1 regularized logistic regression, in
*AAAI*, vol. 6 (2006), pp. 401–408Google Scholar - 25.S. Perkins, J. Theiler, Online feature selection using grafting, in
*Proceedings of the 20th International Conference on Machine Learning (ICML-03)*(2003), pp. 592–599Google Scholar - 26.R. Kohavi et al., A study of cross-validation and bootstrap for accuracy estimation and model selection. in
*Proceedings of International Joint Conference on Artificial Intelligence, IJCAI*, Stanford, CA, vol. 14 (1995), pp. 1137–1145Google Scholar - 27.R.V. Joshi, M. Ziegler, H. Wetter, C. Wandel, H, Ainspan, 14nm finfet based supply voltage boosting techniques for extreme low v min operation, in
*2015 Symposium on VLSI Circuits (VLSI Circuits)*(IEEE, Piscataway, 2015), pp. C268–C269CrossRefGoogle Scholar - 28.R.V. Joshi, M.M. Ziegler, Programmable supply boosting techniques for near threshold and wide operating voltage SRAM, in
*2017 IEEE Custom Integrated Circuits Conference (CICC)*(IEEE, Piscataway, 2017), pp. 1–4Google Scholar - 29.R. Joshi, R. Kanj, S. Nassif, D. Plass, Y. Chan et al., Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell, in
*Proceeding of the 36th European Solid-State Device Research Conference, 2006. ESSDERC 2006*(IEEE, Piscataway, 2006), pp. 315–318Google Scholar