Microprocessor Testing

  • Heather QuinnEmail author


Traditionally, satellites use radiation-hardened microprocessors for on-orbit computation. For many satellites commercial microprocessors could provide smaller, faster, and less power consuming options for on-orbit processing, as long as the mission can tolerate the increased risk. Unfortunately, most commercial microprocessors are not qualified for space usage, and it is up to the organization to determine good candidate parts and qualify them for for space. The qualification process includes testing the microprocessor for single-event effects that can disrupt the computation through silent data corruption and crashes. In this chapter, the fault models for how single-event effects affect computation are introduced so that radiation testers can determine what needs to be tested. Once the test goals are determined, different test protocols and designs are presented as options for testing a variety of microprocessor sub-systems. Currently, there are a number of issues with testing microprocessors, including programming languages, compilers/interpreters, algorithm design, operating systems, and fault injection. These topics are covered in the later part of the chapter.


  1. 1.
    J.L. Hennessy, D.A. Patterson, Computer Architecture: A Quantitative Approach, 6th edn. (Morgan Kaufmann, Waltham, MA, 2017)Google Scholar
  2. 2.
  3. 3.
    Inductiveload, “Pipline MIPs,” (ed.) Wikimedia, 2009, pp. The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture)Google Scholar
  4. 4.
    H. Quinn, T. Fairbanks, J.L. Tripp, A. Manuzzato, The reliability of software algorithms and software-based mitigation techniques in digital signal processors, in Presented at the NSREC, 2013Google Scholar
  5. 5.
    J. Azambuja, F. Sousa, L. Rosa, F. Kastensmidt, The limitations of software signature and basic block sizing in soft error fault coverage, in Presented at the 11th Latin America Test Workshop (LATW), 2010Google Scholar
  6. 6.
    G. Torres, Inside Pentium 4 Architecture, 2005.
  7. 7.
    md-rezaur-rahman, Intel® Xeon Phi™ Core Micro-architecture, 2013.
  8. 8.
    C.J. Wells, The Central Processing Unit (CPU), 2009.
  9. 9.
    F. Irom, Guideline for Ground Radiation Testing of Microprocessors in the Space Radiation Environment. JPL, 2008.
  10. 10.
    S. M. Guertin, B. Wie, M.K. Plante, A. Berkley, L.S. Walling, M. Cabanas-Holmen, SEE test results for maestro microprocessor, in RADECs, 2012Google Scholar
  11. 11.
    H. Quinn, T. Fairbanks, J.L. Tripp, G. Duran, B. Lopez, Single-event effects in low-cost, low-power microprocessors, in NSREC, 2014Google Scholar
  12. 12.
    H. Quinn, Challenges in testing complex systems. IEEE Trans. Nucl. Sci. 61, 766–786 (2014)CrossRefGoogle Scholar
  13. 13.
    P. Rech, T.D. Fairbanks, H.M. Quinn, L. Carro, Threads distribution effects on graphics processing units neutron sensitivity. IEEE Trans. Nucl. Sci. 60, 4220–4225 (2013)CrossRefGoogle Scholar
  14. 14.
    C. Lunardi, H. Quinn, L. Monroe, D. Oliveira, P. Navaux, P. Rech, Experimental and analytical analysis of sorting algorithms error criticality for HPC and large servers applications. IEEE Trans. Nucl. Sci. 64, 2169–2178 (2017)Google Scholar
  15. 15.
    F.M. Lins, L.A. Tambara, F.L. Kastensmidt, P. Rech, Register file criticality and compiler optimization effects on embedded microprocessor reliability. IEEE Trans. Nucl. Sci. 64, 2179–2187 (2017)Google Scholar
  16. 16.
    M. Wirthlin, private communication, 2016.Google Scholar
  17. 17.
    Mantevo Project, 2018.
  18. 18.
    C. Hafer et al., LEON 3FT processor radiation effects data, in Presented at the IEEE Radiation Effects Data Workshop, Quebec City, QC, 2009Google Scholar
  19. 19.
    D.A.G. de Oliveira, L.L. Pilla, T. Santini, P. Rech, Evaluation and mitigation of radiation-induced soft errors in graphics processing units. IEEE Trans. Comput. 65, 791–804 (2016)MathSciNetCrossRefGoogle Scholar
  20. 20.
    M. Wirthlin, D. Lee, G. Swift, H. Quinn, A method and case study on identifying physically adjacent multiple-cell upsets using 28-nm, interleaved and SECDED-protected arrays. IEEE Trans. Nucl. Sci. 61, 3080–3087 (2014)CrossRefGoogle Scholar
  21. 21.
    H. Quinn. Microcontroller Benchmark Codes.
  22. 22.
    H. Quinn, Z. Baker, T. Fairbanks, J.L. Tripp, G. Duran, Robust duplication with comparison methods in microcontrollers. IEEE Trans. Nucl. Sci. 64, 338–345 (2017)CrossRefGoogle Scholar
  23. 23.
    L.D. Edmonds, Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices, JPL, 2009.
  24. 24.
    D.M. Hiemstra, A. Baril, Single event upset characterization of the Pentium(R) MMX and Celeron(R) microprocessors using proton irradiation, in Presented at the Radiation Effects Data Workshop, 2000Google Scholar
  25. 25.
    H. Wang, Q. Chen, L. Chen, D.M. Hiemstra, V. Kirischian, Single event upset characterization of the Tegra K1 Mobile processor using proton irradiation, in Presented at the NSREC, 2017Google Scholar
  26. 26.
    H. Quinn et al., Using benchmarks for radiation testing of microprocessors and FPGAs. IEEE Trans. Nucl. Sci. 62, 2547–2554 (2015)CrossRefGoogle Scholar
  27. 27.
    Politecnico di Torino ITC’99 benchkmarks.
  28. 28.
    T. Ooura, Ooura’s Mathematical Software Packages.
  29. 29.
    Mitigation Working Group,
  30. 30.
    S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in Presented at the International Symposium Microarchitecture (MICRO-36), 2003Google Scholar
  31. 31.
    V. Sridharan, D.R. Kaeli, Eliminating microarchitectural dependency from architectural vulnerability, in Presented at the 15th International Symposium High-Performance Computer Architecture (HPCA-15), 2009Google Scholar
  32. 32.
    R. Velazco, S. Rezgui, R. Ecoffet, Predicting error rate for microprocessor-based digital architectures through CEU (code emulating upsets) injection. IEEE Trans. Nucl. Sci. 47, 2405–2411 (2000)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Space Data Systems and SciencesLos Alamos National LaboratoryLos AlamosUSA

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