Abstract
The emergence of new annealing hardware in the last decade and its potential for efficiently solving NP hard problems in quadratically unconstrained binary optimization (QUBO) by emulating the ground state search of an Ising model are likely to become an important paradigm in natural computing. Driven by the need to parsimoniously exploit the limited hardware resources of present day and near-term annealers, we present a heuristic for constructing graph minors by means of simulated annealing. We demonstrate that our algorithm improves on state of the art hardware embeddings, allowing for the representation of certain QUBO problems with up to 50% more binary variables.
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Notes
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We create random graphs by growing a tree up to the desired number of vertices. To this end we add one vertex at a time and connect it to one of the existing vertices with equal probability. Subsequently, we add edges to the tree, by filling unoccupied edges with equal probability until the prescribed edge density is reached.
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Acknowledgements
It is our pleasure to thank Hirofumi Suzuki, Kazuhiro Kurita, and Shoya Takahashi for supporting the organization of the “Hokkaido University & Hitachi 2nd New-Concept Computing Contest 2017.”
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Sugie, Y. et al. (2018). Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. In: Fagan, D., Martín-Vide, C., O'Neill, M., Vega-Rodríguez, M.A. (eds) Theory and Practice of Natural Computing. TPNC 2018. Lecture Notes in Computer Science(), vol 11324. Springer, Cham. https://doi.org/10.1007/978-3-030-04070-3_9
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DOI: https://doi.org/10.1007/978-3-030-04070-3_9
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