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180 Mbps Viterbi Decoder Design on FPGA for OFDM Modulator in Underwater Communication Applications

  • N. GirishEmail author
  • M. B. Veena
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)

Abstract

Underwater communication channels are designed to provide maximum data rate and its based on OFDM modules. Error coding which is an integral part of OFDM performs the process of error encoding and message decoding by convolution encoding and viterbi decoding respectively. With low power design requirement of OFDM modules for underwater applications, viterbi decoder iterative logic is designed and implemented on FPGA. The novel architecture for viterbi decoder is basically on LUT approach and direct decoding method. The dynamic reconfiguration of such a decoder works on threshold logic that is set with two threshold levels. The design implemented on FPGA is found to operate upto 188 Mbps data rate consuming less than 680 mW of power dissipation.

Keywords

Viterbi decoder Underwater communication (UWC) FPGA Error coding High speed 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.BMS College of EngineeringBangaloreIndia

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