Design of Low Power RSC Encoder Using Reversible Logic

  • J. Aishvarya
  • P. S. N. V. V. Sai Manindra
  • P. Sathya Priya
  • Kruthi Vaseeshwar Rao
  • E. PrabhuEmail author
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 26)


The principal theme in present world of electronic is low power design. In modern technologies, low power design has drawn significant concern due to increasing transistor counts, higher speed of operations and clock frequencies. Reversible logic plays a vital role when VLSI circuits with minimal power dissipation are considered. It has the ability to decrease the power dissipation by recuperating bit loss from its distinctive one to one mapping. This paper presents a novel design of Recursive Systematic Convolutional (RSC) Encoder using the existing reversible gates. The proposed RSC encoder is coded in Verilog-HDL and synthesized in synopsis DC tool (90 nm library). The power analysis report shows that the proposed RSC encoder circuit dissipates less power when compared to the conventional one.


Low power RSC encoder Reversible logic 


  1. 1.
    Keyes, R., Landauer, R.: Minimal energy dissipation in logic. IBM J. Res. Dev. 14, 152–157 (1970)CrossRefGoogle Scholar
  2. 2.
    Moore, G.E.: Cramming more components onto integrated circuits. J. Electron. 38(8), 114–117 (1965)Google Scholar
  3. 3.
    Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)MathSciNetCrossRefGoogle Scholar
  4. 4.
    Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)zbMATHGoogle Scholar
  5. 5.
    Schrom, G.: Ultra-low-power CMOS Technology. Ph.D. thesis, Technischen Universitat Wien, June 1998Google Scholar
  6. 6.
    Kerntopf, P., Perkowski, M., Khan, M.H.A.: On universality of general reversible multiple valued logic gates. In: IEEE Proceedings of the 34th International Symposium on Multiple Valued Logic (ISMVL04), pp. 68–73 (2004)Google Scholar
  7. 7.
    Perkowski, M., et al.: A Hierarchical approach to computer-aided design of quantum circuits. In: Proceedings of 6th International Symposium on Representations and Methodology of Future Computing Technology, RM 2003, Trier, Germany, 10–11 March, pp. 201–209 (2003)Google Scholar
  8. 8.
    Biswas, A.K., Hasan, M.M., Chowdhury, A.R., Babu, H.M.H.: Efficient approaches for designing reversible binary coded decimal adders. Microelectron. J. 39(12), 1693–1703 (2008)CrossRefGoogle Scholar
  9. 9.
    Prabhu, E., Mangalam, H., Karthick, S.: Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic. J. Cent. South Univ. 23(7), 1669–1681 (2016)CrossRefGoogle Scholar
  10. 10.
    Balakumaran, R., Prabhu, E.: Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder. In: 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), Nagercoil, pp. 1–7 (2016)Google Scholar
  11. 11.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183–191 (1961)MathSciNetCrossRefGoogle Scholar
  12. 12.
    Merkle, R.C.: Two types of mechanical reversible logic. Nanotechnology 4, 114–131 (1993)CrossRefGoogle Scholar
  13. 13.
    Reddy, B.M., Prabhu, E.: An efficient 16-Bit carry select adder with optimized power and delay. Int. J. Appl. Eng. Res. 10(11), 27909–27916 (2015)Google Scholar
  14. 14.
    Toffoli, T.: “Reversible Computing,” automata, languages and programming. In: 7th Colloquium of Lecture Notes in Computer Science, vol. 85, pp. 632–644 (1980)CrossRefGoogle Scholar
  15. 15.
    Karthick, S., Valarmathy, S., Prabhu, E.: Low power systolic array based digital filter for DSP applications. Sci. World J. 2015, 1–6 (2015)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • J. Aishvarya
    • 1
  • P. S. N. V. V. Sai Manindra
    • 1
  • P. Sathya Priya
    • 1
  • Kruthi Vaseeshwar Rao
    • 1
  • E. Prabhu
    • 1
    Email author
  1. 1.Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa VidyapeethamAmrita UniversityCoimbatoreIndia

Personalised recommendations