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Fault Tolerance in 3D-ICs

  • Raviteja P. Reddy
  • Amit AcharyyaEmail author
  • Saqib Khursheed
Chapter
  • 575 Downloads
Part of the Internet of Things book series (ITTCC)

Abstract

The systems with emerging technologies like Internet-of-Things and beyond Von-Neumann architectures can be produced in large scale only if they are resilient-aware, cost-effective and secure. The resilient and cost-effective solutions can be achieved by incorporating fault tolerance techniques at the architecture level of the system design is one of the plausible solutions. The choice of various fault tolerance techniques gives the designers a freedom to incorporate these in the early stage of the design and in turn leading to high yield and reliable architectures. Through-silicon-via (TSV) interconnects based three-dimensional integrated circuits are emerging technologies consisting of vertical communication between the stacked dies, leading to the decrease of wire length and thus enhances the system performance. However, yield and reliability are the major issues that hinder resilient and cost-effective solutions for 3D-IC design. These can be addressed by incorporation of fault tolerance techniques.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Raviteja P. Reddy
    • 1
  • Amit Acharyya
    • 1
    Email author
  • Saqib Khursheed
    • 2
  1. 1.Electrical EngineeringIndian Institute of TechnologyHyderabadIndia
  2. 2.Electrical Engineering and ElectronicsUniversity of LiverpoolLiverpoolUK

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