Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA

  • Durga Prasad Sahoo
  • Arnab BagEmail author
  • Sikhar Patranabis
  • Debdeep Mukhopadhyay
  • Rajat Subhra Chakraborty
Part of the Internet of Things book series (ITTCC)


Most of the faults in circuits or systems occur due to the unintentional but natural phenomenon (e.g. imperfection in manufacturing process or significant change in the working environment), and thus, these faults are often follow a pattern and comparatively easier detect than the intentional faults. In the context of secure design/system, the adversary (intentionally) injects some faults in the system to bypass the security protection or reveal secret information. Since the adversaries’ fault injection objectives are often very subjective, it is difficult to find a pattern among the faults in a system, and this makes the fault detection and fault recovery difficult in a secure system. In this chapter, we discuss possible intentional faults in an emerging hardware security primitive, known as Physically Unclonable Functions (PUFs). We show how the faults vary over the PUF designs and its applications. In addition, we explain different fault detection circuits and fault recovery techniques which are specific to PUF designs and their implementations on FPGA platforms.


  1. 1.
    Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs UG768 (v14.7) October 2, 2013.
  2. 2.
    Xilinx 7 Series FPGAs Configurable Logic Block User Guide UG474 (v1.7) November 17, 2014.
  3. 3.
    Xilinx 7 Series FPGAs Configuration User Guide UG470 (v1.10) June 24, 2015.
  4. 4.
    Xilinx Partial Reconfiguration User Guide UG702 (v14.1) April 24, 2012.
  5. 5.
    Barenghi, A., Breveglieri, L., Koren, I., Naccache, D.: Fault injection attacks on cryptographic devices: theory, practice, and countermeasures. Proc. IEEE 100(11), 3056–3076 (2012). Scholar
  6. 6.
    Bartolini, D.B., Carminati, M., Cancare, F., Santambrogio, M.D., Sciuto, D.: HERA project’s holistic evolutionary framework. In: Proceedings of IEEE International Symposium on Parallel & Distributed Workshops, pp. 231–238 (2013).
  7. 7.
    Becker, G.T.: The gap between promise and reality: on the insecurity of XOR Arbiter PUFs. In: Proceedings of 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES) (2015)Google Scholar
  8. 8.
    Cancare, F., Bartolini, D.B., Carminati, M., Sciuto, D., Santambrogio, M.D.: On the evolution of hardware circuits via reconfigurable architectures. ACM Trans. Reconfig. Technol. Syst. (TRETS) 5(4), 22 (2012). Scholar
  9. 9.
    Chen, Q., Csaba, G., Lugli, P., Schlichtmann, U., ührmair, U.R.: The bistable ring PUF: a new architecture for strong physical unclonable functions. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 134 –141 (2011)Google Scholar
  10. 10.
    Cherif, Z., Danger, J.L., Guilley, S., Bossuet, L.: An easy-to-design PUF based on a single oscillator: the loop PUF. In: Proceedings of 15th Euromicro Conference on Digital System Design (DSD), pp. 156–162 (2012)Google Scholar
  11. 11.
    Delvaux, J., Verbauwhede, I.: Fault injection modeling attacks on 65 nm Arbiter and RO Sum PUFs via environmental changes. IACR Cryptol. ePrint Archive 2013, 619 (2013)Google Scholar
  12. 12.
    Delvaux, J., Verbauwhede, I.: Side channel modeling attacks on 65 nm Arbiter PUFs exploiting CMOS device noise. In: IEEE 6th International Symposium on Hardware-Oriented Security and Trust (2013)Google Scholar
  13. 13.
    Ganji, F., Krämer, J., Seifert, J., Tajik, S.: Lattice basis reduction attack against physically unclonable functions. In: Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security (CCS), pp. 1070–1080 (2015)Google Scholar
  14. 14.
    Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)MathSciNetCrossRefGoogle Scholar
  15. 15.
    Karaklajic, D., Schmidt, J., Verbauwhede, I.: Hardware designer’s guide to fault attacks. IEEE Trans. VLSI Syst. 21(12), 2295–2306 (2013)CrossRefGoogle Scholar
  16. 16.
    Koçabas, Ü., Peter, A., Katzenbeisser, S., Sadeghi, A.: Converse PUF-based authentication. In: Trust and Trustworthy Computing—5th International Conference, TRUST 2012, Vienna, Austria, 13–15 June 2012. Proceedings, pp. 142–158 (2012)Google Scholar
  17. 17.
    Lai, V., Diessel, O.: ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs. In: Proceedings of International Conference on Field-Programmable Technology (FPT), pp. 357–360 (2009).
  18. 18.
    Lim, D.: Extracting Secret Keys from Integrated Circuits. Master’s thesis, MIT, USA (2004)Google Scholar
  19. 19.
    Maes, R.: Physically Unclonable Functions—Constructions, Properties and Applications. Springer (2013)Google Scholar
  20. 20.
    Maes, R., van der Leest, V., van der Sluis, E., Willems, F.: Secure key generation from biased PUFs. In: Proceedings of 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp. 517–534 (2015)Google Scholar
  21. 21.
    Maiti, A., Nagesh, R., Reddy, A., Schaumont, P.: Physical unclonable function and true random number generator: a compact and scalable implementation. In: Proceedings of ACM Great Lakes Symposium on VLSI, pp. 425–428 (2009)Google Scholar
  22. 22.
    Maiti, A., Gunreddy, V., Schaumont, P.: A systematic method to evaluate and compare the performance of physical unclonable functions. IACR Cryptol. ePrint Archive 2011, 657 (2011)Google Scholar
  23. 23.
    Majzoobi, M., Koushanfar, F., Devadas, S.: FPGA PUF using programmable delay lines. In: IEEE International Workshop on Information Forensics and Security (WIFS), pp. 1–6 (2010)Google Scholar
  24. 24.
    Majzoobi, M., Rostami, M., Koushanfar, F., Wallach, D.S., Devadas, S.: Slender PUF protocol: a lightweight, robust, and secure authentication by substring matching. In: Proceedings of IEEE Symposium on Security and Privacy Workshops, pp. 33–44 (2012)Google Scholar
  25. 25.
    Malkin, T., Standaert, F., Yung, M.: A comparative cost/security analysis of fault attack countermeasures. In: Proceedings of Fault Diagnosis and Tolerance in Cryptography (FDTC), pp. 159–172 (2006)Google Scholar
  26. 26.
    Merli, D., Schuster, D., Stumpf, F., Sigl, G.: Semi-invasive EM attack on FPGA RO PUFs and countermeasures. In: Proceedings of the 6th Workshop on Embedded Systems Security (WESS 2011) (2011)Google Scholar
  27. 27.
    Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. In: Proceedings of 17th ACM Conference on Computer and Communications Security (CCS), pp. 237–249. ACM, New York, NY, USA (2010)Google Scholar
  28. 28.
    Rührmair, U., Sölter, J., Sehnke, F., Xu, X., Mahmoud, A., Stoyanova, V., Dror, G., Schmidhuber, J., Burleson, W., Devadas, S.: PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8(11), 1876–1891 (2013)CrossRefGoogle Scholar
  29. 29.
    Rührmair, U., Xu, X., Sölter, J., Mahmoud, A., Majzoobi, M., Koushanfar, F., Burleson, W.P.: Efficient power and timing side channels for physical unclonable functions. In: Proceedings of 16th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp. 476–492 (2014)CrossRefGoogle Scholar
  30. 30.
    Sahoo, D.P.: Design and Analysis of Secure Physically Unclonable Function Compositions. Ph.D. thesis (2017)Google Scholar
  31. 31.
    Sahoo, D.P., Saha, S., Mukhopadhyay, D., Chakraborty, R.S., Kapoor, H.: Composite PUF: a new design paradigm for physically unclonable functions on FPGA. In: Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 50–55 (2014)Google Scholar
  32. 32.
    Sahoo, D.P., Mukhopadhyay, D., Chakraborty, R.S., Nguyen, P.H.: A multiplexer-based Arbiter PUF composition with enhanced reliability and security. IEEE Trans. Comput. 67(3), 403–417 (2018). Scholar
  33. 33.
    Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of Design Automation Conference (DAC), pp. 9–14. ACM Press, New York, NY, USA (2007)Google Scholar
  34. 34.
    Tajik, S., Dietz, E., Frohmann, S., Seifert, J., Nedospasov, D., Helfmeier, C., Boit, C., Dittrich, H.: Physical characterization of Arbiter PUFs. In: Proceedings of 16th International Workshop Cryptographic Hardware and Embedded Systems (CHES), pp. 493–509 (2014)CrossRefGoogle Scholar
  35. 35.
    Tajik, S., Lohrke, H., Ganji, F., Seifert, J.P., Boit, C.: Laser fault attack on physically unclonable functions. In: Proceedings of 12th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC) (2015)Google Scholar
  36. 36.
    Tobisch, J., Becker, G.T.: On the scaling of machine learning attacks on PUFs with application to noise bifurcation. In: Proceedings of 11th International Workshop on Radio Frequency Identification: Security and Privacy Issues (RFIDsec), pp. 17–31 (2015)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Durga Prasad Sahoo
    • 1
  • Arnab Bag
    • 2
    Email author
  • Sikhar Patranabis
    • 2
  • Debdeep Mukhopadhyay
    • 2
  • Rajat Subhra Chakraborty
    • 2
  1. 1.Bosch India (RBEI/ESY)BengaluruIndia
  2. 2.IIT KharagpurKharagpurIndia

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