Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach

  • Vladimir HerdtEmail author
  • Hoang M. Le
  • Daniel Große
  • Rolf Drechsler
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 530)


Efficient power management is very important for modern System-on-Chip to satisfy the conflicting demands on high performance and low power consumption. Nowadays, global power management is mostly implemented in firmware (FW) due to the relative ease of development and its flexibility. Recent advances in system-level power modeling and estimation open up opportunities for early validation of these FW-based power management strategies. In this paper, we propose a novel approach for this purpose using SystemC-based Virtual Prototypes (VPs) and constrained random (CR) techniques. The CR-generated representative system workloads are executed in a power-aware FW/VP co-simulation to validate that available performance and power budgets are satisfied. As a proof-of-concept, we demonstrate our power validation approach on the LEON3-based SoCRocket VP.


Validation Power management Virtual prototype SystemC TLM Firmware Constrained random Simulation ESL VP 


  1. 1.
    HW-SW, SystemC co-simulation SoC validation platform. Technical Report, TU Braunschweig (2012)Google Scholar
  2. 2.
    B. Bailey, Power limits of EDA (2016).
  3. 3.
    D. Große, R. Drechsler, Quality-Driven SystemC Design. (Springer, Dordrecht, 2010)CrossRefGoogle Scholar
  4. 4.
    K. Grüttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero, R. Valencia, The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. Microprocess. Microsyst. 37(8, Part C), 966–980 (2013)CrossRefGoogle Scholar
  5. 5.
    F. Haedicke, H.M. Le, D. Große, R. Drechsler, CRAVE: an advanced constrained random verification environment for SystemC, in ISSoC, 2012, pp. 1–7Google Scholar
  6. 6.
    M. Hassan, V. Herdt, H.M. Le, M. Chen, D. Große, R. Drechsler, Data flow testing for virtual prototypes, in DATE, 2017, pp. 380–385Google Scholar
  7. 7.
    M. Hassan, V. Herdt, H.M. Le, D. Große, R. Drechsler, Early SoC security validation by VP-based static information flow analysis, in ICCAD, 2017, pp. 400–407Google Scholar
  8. 8.
    V. Herdt, H.M. Le, D. Große, R. Drechsler, Compiled symbolic simulation for SystemC, in ICCAD, 2016, pp. 52:1–52:8Google Scholar
  9. 9.
    V. Herdt, H.M. Le, D. Große, R. Drechsler, On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation – a case study, in FDL (2016), pp. 1–8Google Scholar
  10. 10.
    V. Herdt, H.M. Le, D. Große, R. Drechsler, ParCoSS: efficient parallelized compiled symbolic simulation, in CAV 2016, pp. 177–183Google Scholar
  11. 11.
    V. Herdt, H.M. Le, D. Große, R. Drechsler, Verifying SystemC using intermediate verification language and stateful symbolic simulation. TCAD (2018).
  12. 12.
    IEEE Std. 1666: IEEE Standard SystemC Language Reference Manual (2011)Google Scholar
  13. 13.
    J. Karmann, W. Ecker, The semantic of the power intent format UPF: consistent power modeling from system level to implementation, in PATMOS Workshop, 2013, pp. 45–50Google Scholar
  14. 14.
    J. Laurent, N. Julien, E. Senn, E. Martin, Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, in DATE, vol. 1, 2004, pp. 666–667Google Scholar
  15. 15.
    H.M. Le, R. Drechsler, CRAVE 2.0: the next generation constrained random stimuli generator for SystemC, in DVCon, 2014Google Scholar
  16. 16.
    H.M. Le, V. Herdt, D. Große, R. Drechsler, Towards formal verification of real-world SystemC TLM peripheral models – a case study, in DATE, 2016, pp. 1160–1163Google Scholar
  17. 17.
    O. Mbarek, A. Pegatoquet, M. Auguin, Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level. IET Circuits Dev. Syst. 6(5), 287–296 (2012)CrossRefGoogle Scholar
  18. 18.
    G. Onnebrink, R. Leupers, G. Ascheid, S. Schürmans, Black box ESL power estimation for loosely-timed TLM models. in SAMOS, 2016, pp. 366–371.
  19. 19.
    S.K. Rethinagiri, O. Palomar, R. Ben Atitallah, S. Niar, O. Unsal, A.C. Kestelman, System-level power estimation tool for embedded processor based platforms, in RAPIDO Workshop, 2014, pp. 5:1–5:8Google Scholar
  20. 20.
    P. Sayyah, M.T. Lazarescu, S. Bocchio, E. Ebeid, G. Palermo, D. Quaglia, A. Rosti, L. Lavagno, Virtual platform-based design space exploration of power-efficient distributed embedded applications. TECS 14(3), 49:1–49:25 (2015)CrossRefGoogle Scholar
  21. 21.
    S. Schürmans, D. Zhang, D. Auras, R. Leupers, G. Ascheid, X. Chen, L. Wang, Creation of ESL power models for communication architectures using automatic calibration, in DAC, 2013, pp. 1–6.
  22. 22.
    T. Schuster, R. Meyer, R. Buchty, L. Fossati, M. Berekovic, Socrocket – a virtual platform for the European Space Agency’s SoC development, in ReCoSoC, 2014, pp. 1–7Google Scholar
  23. 23.
    B. Wang, Y. Xu, R. Hasholzner, C. Drewes, R. Rosales, S. Graf, J. Falk, M. Glaß, J. Teich, Exploration of power domain partitioning for application-specific SoCs in system-level design, in MBMV Workshop, 2016, pp. 102–113Google Scholar
  24. 24.
    W. Ye, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, The design and use of simplepower: a cycle-accurate energy estimation tool, in DAC, 2000, pp. 340–345Google Scholar
  25. 25.
    J. Yuan, C. Pixley, A. Aziz, Constraint-Based Verification. (Springer, New York, 2006)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Vladimir Herdt
    • 1
    Email author
  • Hoang M. Le
    • 1
  • Daniel Große
    • 2
  • Rolf Drechsler
    • 2
  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany
  2. 2.Institute of Computer ScienceUniversity of Bremen and Cyber-Physical Systems, DFKI GmbHBremenGermany

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