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Temporal Logic Verification of Stochastic Systems Using Barrier Certificates

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Automated Technology for Verification and Analysis (ATVA 2018)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 11138))

Abstract

This paper presents a methodology for temporal logic verification of discrete-time stochastic systems. Our goal is to find a lower bound on the probability that a complex temporal property is satisfied by finite traces of the system. Desired temporal properties of the system are expressed using a fragment of linear temporal logic, called safe LTL over finite traces. We propose to use barrier certificates for computations of such lower bounds, which is computationally much more efficient than the existing discretization-based approaches. The new approach is discretization-free and does not suffer from the curse of dimensionality caused by discretizing state sets. The proposed approach relies on decomposing the negation of the specification into a union of sequential reachabilities and then using barrier certificates to compute upper bounds for these reachability probabilities. We demonstrate the effectiveness of the proposed approach on case studies with linear and polynomial dynamics.

This work was supported in part by the German Research Foundation (DFG) through the grant ZA 873/1-1 and the TUM International Graduate School of Science and Engineering (IGSSE).

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Authors and Affiliations

  1. Technical University of Munich, Munich, Germany

    Pushpak Jagtap & Majid Zamani

  2. Newcastle University, Newcastle upon Tyne, United Kingdom

    Sadegh Soudjani

Authors
  1. Pushpak Jagtap
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  2. Sadegh Soudjani
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  3. Majid Zamani
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Correspondence to Sadegh Soudjani .

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Editors and Affiliations

  1. Microsoft Research, Redmond, WA, USA

    Shuvendu K. Lahiri

  2. University of Southern California, Los Angeles, CA, USA

    Chao Wang

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Jagtap, P., Soudjani, S., Zamani, M. (2018). Temporal Logic Verification of Stochastic Systems Using Barrier Certificates. In: Lahiri, S., Wang, C. (eds) Automated Technology for Verification and Analysis. ATVA 2018. Lecture Notes in Computer Science(), vol 11138. Springer, Cham. https://doi.org/10.1007/978-3-030-01090-4_11

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  • DOI: https://doi.org/10.1007/978-3-030-01090-4_11

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