Abstract
Multipliers play an imperative role in communication, signal and image processing, and embedded ASICs. Generally, multipliers are designed through various steps and they are occupying more area in the hardware, consumes more power, and causes an effect on performance. This paper is aimed to implement low-area and high-speed multiplier using various data compressors in partial product stages and tested for image processing. To suppress the vertical dimension of the partial product stage in multiplier, Sklansky adder is considered for the last stage and five hybrid multiplier architectures (HyMUL1–HyMUL5) have been implemented. For application verification, the two grayscale images are given as the inputs of the proposed multipliers and produce a new image which is an overlap of the two input images. The comparative analysis indicates that the proposed multiplier HyMUL2 consumed less area compared to other multipliers and its speed is also improved. The obtained new overlapped image using proposed multiplier HyMUL2 has high PSNR and low NMED.
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Saravanakumar, U., Suresh, P., Karthikeyan, V. (2019). Low-Power High-Speed Hybrid Multiplier Architectures for Image Processing Applications. In: Pandian, D., Fernando, X., Baig, Z., Shi, F. (eds) Proceedings of the International Conference on ISMAC in Computational Vision and Bio-Engineering 2018 (ISMAC-CVB). ISMAC 2018. Lecture Notes in Computational Vision and Biomechanics, vol 30. Springer, Cham. https://doi.org/10.1007/978-3-030-00665-5_54
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DOI: https://doi.org/10.1007/978-3-030-00665-5_54
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