The success of SPIN in industrial software development is primarily due to the efficiency with which it carries out verifications. The efficiency results in part from the architecture of SPIN (Figure 2.1), which generates a verifier that is optimized for a particular model, correctness specification, and search method. The verifier is written in C, a relatively low-level language that can be optimized by compilers. Nevertheless, even the most efficient verifier will run up against limitations of time and memory, so that the task of the systems engineer is to find the appropriate tradeoffs between model complexity and resources. SPIN supports various ways of optimizing the use of resources, in particular, memory.

To profit from these options you must have a basic understanding of how SPIN verifies models written in PROMELA; we give an overview of this topic in Section 10.1. Section 10.2 surveys techniques for optimizing verifications in SPIN. Section 10.3 describes how correctness specifications in temporal logic are translated into never claims in PROMELA, and Section 10.4 presents non-progress cycles, an alternate technique for verifying liveness properties.

If you intend to use any of the constructs introduced in this chapter, you should read their full description in SMC or the man pages.

A prerequisite for understanding the material in this chapter is a basic familiarity with data structures such as directed graphs and hash tables.


State Vector Temporal Logic Hash Table Critical Section Mutual Exclusion 
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© Springer-Verlag London Limited 2008

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