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Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors

Chapter

Abstract

To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip-multi-processors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network into subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50 % lower latency at low loads and ∼ 40 % higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies ∼ 40 % versus an electrical 2D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite.

Keywords

Waveguide Length Silicon Waveguide Realistic Workload Arbitration Scheme Credit Return 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.HP LaboratoriesPalo AltoUSA
  2. 2.Texas A&M UniversityCollege StationUSA

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