Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors



To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip-multi-processors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network into subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50 % lower latency at low loads and ∼ 40 % higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies ∼ 40 % versus an electrical 2D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite.


Waveguide Length Silicon Waveguide Realistic Workload Arbitration Scheme Credit Return 
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  1. 1.
    Howard J, Dighe S, Vangal SR, Ruhl G, Borkar N, Jain S, Erraguntla V, Konow M, Riepen M, Gries M, Droege G, Lund-Larsen T, Steibl S, Borkar S, De VK, Wijngaart RVD. A 48-Core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J Solid-State Circuits. 2011;46:173–83.CrossRefGoogle Scholar
  2. 2.
    Anders M, Kaul H, Hsu S, Agarwal A, Mathew S, Sheikh F, Krishnamurthy R, Borkar S. A 4.1 Tb/s bisection-bandwidth 560 Gb/s/W streaming circuit-switched mesh network-on-chip in 45 nm cmos. In: 2010 IEEE international solid-state circuits conference digest of technical papers (ISSCC), 2010. pp. 110–1.Google Scholar
  3. 3.
    Kim J, Park D, Theocharides T, Vijaykrishnan N, Das CR. A Low Latency Router Supporting Adaptivity for On-Chip Interconnects. In: 2005 Design automation conference, 2005. pp. 559–64.Google Scholar
  4. 4.
    Lipson M. Compact electro-optic modulators on a silicon chip. IEEE J Sel Top Quantum Electron. 2006;12(6):1520–6.CrossRefGoogle Scholar
  5. 5.
    Liu A, Liao L, Rubin D, Nguyen H, Ciftcioglu B, Chetrit Y, Izhaky N, Paniccia M. High-speed optical modulation based on carrier depletion in a silicon waveguide. Opt Express. 2007;15(2):660–8.CrossRefGoogle Scholar
  6. 6.
    Reshotko M, Block B, Jin B, Chang P. Waveguide coupled Ge-on-oxide photodetectors for integrated optical links. In: The 2008 5th IEEE international conference on group IV photonics, 2008. pp. 182–4.Google Scholar
  7. 7.
    Holzwarth C, Orcutt J, Li H, Popovic M, Stojanovic V, Hoyt J, Ram R, Smith H. Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes. In: Conference on lasers and electro-optics, 2008. pp. 1–2.Google Scholar
  8. 8.
    Kimerling LC, Ahn D, Apsel A, Beals M, Carothers D, Chen Y-K, Conway T, Gill DM, Grove M, Hong C-Y, Lipson M, Michel J, Pan D, Patel SS, Pomerene AT, Rasras M, Sparacin DK, Tu K-Y, White AE, Wong CW. Electronic-photonic integrated circuits on the CMOS platform. In: Silicon photonics, 2006. pp. 6–15.Google Scholar
  9. 9.
    Narasimha A, Analui B, Liang Y, Sleboda T, Gunn C. A fully integrated 4–10-Gb/s DWDM optoelectronic transceiver implemented in a standard 0.13 m CMOS SOI technology. In: The IEEE international solid-state circuits conference, 2007. pp. 42–586.Google Scholar
  10. 10.
    Young I, Mohammed E, Liao J, Kern A, Palermo S, Block B, Reshotko M, Chang P. Optical I/O technology for tera-scale computing. In: The IEEE international solid-state circuits conference, 2009. pp. 468–9.Google Scholar
  11. 11.
    Hendry G, Kamil S, Biberman A, Chan J, Lee B, Mohiyuddin M, Jain A, Bergman K, Carloni L, Kubiatowicz J, Oliker L, Shalf J. Analysis of photonic networks for a chip multiprocessor using scientific applications. In: The 3rd ACM/IEEE international symposium on networks-on-chip (NOCS), 2009. pp. 104–13.Google Scholar
  12. 12.
    Shacham A, Bergman K, Carloni LP. On the design of a photonic network-on-chip. In: The first international symposium on networks-on-chip (NOCS), 2007. pp. 53–64.Google Scholar
  13. 13.
    Shacham A, Bergman K, Carloni LP. Photonic NoC for DMA communications in chip multiprocessors. In: The 15th annual IEEE symposium on high-performance interconnects, 2007. pp. 29–38.Google Scholar
  14. 14.
    Shacham A, Bergman K, Carloni LP. Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans Comput. 2008;57(9):1246–60.CrossRefMathSciNetGoogle Scholar
  15. 15.
    Joshi A, Batten C, Kwon Y-J, Beamer S, Shamim I, Asanovic K, Stojanovic V. Silicon-photonic clos networks for global on-chip communication. In: The 2009 3rd ACM/IEEE international symposium on networks-on-chip (NOCS), 2009. pp. 124–33.Google Scholar
  16. 16.
    Kirman N, Kirman M, Dokania R, Martinez J, Apsel A, Watkins M, Albonesi D. Leveraging optical technology in future bus-based chip multiprocessors. In: The 39th annual IEEE/ACM international symposium on microarchitecture (Micro), 2006. pp. 492–503.Google Scholar
  17. 17.
    Krishnamoorthy A, Ho R, Zheng X, Schwetman H, Lexau J, Koka P, Li G, Shubin I, Cunningham J. Computer systems based on silicon photonic interconnects. Proc IEEE. 2009;97(7):1337–61.CrossRefGoogle Scholar
  18. 18.
    Pan Y, Kim J, Memik G. FlexiShare: channel sharing for an energy-efficient nanophotonic crossbar. In: The 16th IEEE international symposium on high performance computer architecture (HPCA), 2010. pp. 1–12.Google Scholar
  19. 19.
    Pan Y, Kumar P, Kim J, Memik G, Zhang Y, Choudhary A. Firefly: illuminating future network-on-chip with nanophotonics. In: 36th International symposium on computer architecture (ISCA), 2009.Google Scholar
  20. 20.
    Vantrease D, Binkert N, Schreiber R, Lipasti MH. Light speed arbitration and flow control for nanophotonic interconnects. In: 42nd Annual IEEE/ACM international symposium on microarchitecture, 2009. pp. 304–15.Google Scholar
  21. 21.
    Vantrease D, Schreiber R, Monchiero M, McLaren M, Jouppi NP, Fiorentino M, Davis A, Binkert N, Beausoleil RG, Ahn JH. Corona: system implications of emerging nanophotonic technology. In: 35th International symposium on computer architecture (ISCA), 2008. pp. 153–64.Google Scholar
  22. 22.
    Koka P, McCracken MO, Schwetman H, Zheng X, Ho R, Krishnamoorthy AV. Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. In: 37th International symposium on computer architecture (ISCA), 2010. pp. 117–28.Google Scholar
  23. 23.
    Kao YH, Chao HJ, BLOCON: a bufferless photonic clos network-on-chip architecture. In: 5th ACM/IEEE international symposium on networks-on-chip (NoCS), 2011. pp. 81–8.Google Scholar
  24. 24.
    Li C, Browning M, Gratz PV, Palermo S. Luminoc: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures. In: Proceedings of the 21st international conference on parallel architectures and compilation techniques, PACT ’12, (New York, NY, USA), ACM, 2012. pp. 421–2.Google Scholar
  25. 25.
    Young I, Mohammed E, Liao J, Kern A, Palermo S, Block B, Reshotko M, Chang P. Optical I/O technology for tera-scale computing. IEEE J Solid State Circuits. 2010;45:235–48.CrossRefGoogle Scholar
  26. 26.
    Lee BG, Rylyakov AV, Green WMJ, Assefa S, Baks CW, Rimolo-Donadio R, Kuchta DM, Khater MH, Barwicz T, Reinholm C, Kiewra E, Shank SM, Schow CL, Vlasov YA. Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits. In: IEEE-OSA optical fiber communications conference, 2013. pp. 1–3.Google Scholar
  27. 27.
    Roth JE, Palermo S, Helman NC, Bour DP, Miller DAB, Horowitz M. An optical interconnect transceiver at 1550 nm using low-voltage electroabsorption modulators directly integrated to CMOS. IEEE-OSA J Lightwave Technol. 2007;25:3739–47.CrossRefGoogle Scholar
  28. 28.
    Liu A, Liao L, Rubin D, Basak J, Nguyen H, Chetrit Y, Cohen R, Izhaky N, Paniccia M. High-speed silicon modulator for future vlsi interconnect. In: Integrated photonics and nanophotonics research and applications/slow and fast light, 2007. p. IMD3, Optical Society of America.Google Scholar
  29. 29.
    Wojcik GL, Yin D, Kovsh AR, Gubenko AE, Krestnikov IL, Mikhrin SS, Livshits DA, Fattal DA, Fiorentino M, Beausoleil RG. A single comb laser source for short reach WDM interconnects. In: Society of photo-optical instrumentation engineers (SPIE) conference series. Society of photo-optical instrumentation engineers (SPIE) conference series, vol. 7230, 2009.Google Scholar
  30. 30.
    Soref RA, Bennett B. Electrooptical effects in silicon. IEEE J Quantum Electron. 1987;23:hbox123–9.Google Scholar
  31. 31.
    Li C, Bai R, Shafik A, Tabasy E, Tang G, Ma C, Chen C-H, Peng Z, Fiorentino M, Chiang P, Palermo S. A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver. In 2013 IEEE international solid-state circuits conference digest of technical papers (ISSCC), 2013. pp. 124–5.Google Scholar
  32. 32.
    Li G, Zheng X, Yao J, Thacker H, Shubin I, Luo Y, Raj K, Cunningham JE, Krishnamoorthy AV. High-efficiency 25 Gb/s CMOS ring modulator with integrated thermal tuning. In: 8th IEEE Intentional Conference on Group IV Photonics (GFP), vol. 4, 2011. pp. 8–10.Google Scholar
  33. 33.
    Xu Q, Manipatruni S, Schmidt B, Shakya J, Lipson M. 12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators. Opt. Express. 2007;15:430–6.Google Scholar
  34. 34.
    Chen C-H, Li C, Shafik A, Fiorentino M, Chiang P, Palermo S, Beausoleil R. A wdm silicon photonic transmitter based on carrier-injection microring modulators. In: 2014 IEEE optical interconnects conference, 2014.Google Scholar
  35. 35.
    Liu F, Patil D, Lexau J, Amberg P, Dayringer M, Gainsley J, Moghadam H, Zheng X, Cunningham J, Krishnamoorthy A, Alon E, Ho R. 10-Gbps, 5.3-mW optical transmitter and receiver circuits in 40-nm cmos. IEEE J Solid State Circuits. 2012;47(9):2049–67.Google Scholar
  36. 36.
    Sun C, Timurdogan E, Watts M, Stojanovic V. Integrated microring tuning in deep-trench bulk cmos. In: 2013 IEEE optical interconnects conference, 2013. pp. 54–5.Google Scholar
  37. 37.
    Orcutt JS, Moss B, Sun C, Leu J, Georgas M, Shainline J, Zgraggen E, Li H, Sun J, Weaver M, Urošević S, Popović M, Ram RJ, Stojanović V. Open foundry platform for high-performance electronic-photonic integration. Opt. Express. 2012;20:12222–32.CrossRefGoogle Scholar
  38. 38.
    Dong P, Qian W, Liang H, Shafiiha R, Feng D, Li G, Cunningham JE, Krishnamoorthy AV, Asghari M. Thermally tunable silicon racetrack resonators with ultralow tuning power. Opt. Express. 2010;18:20298–304.CrossRefGoogle Scholar
  39. 39.
    Orcutt JS, Khilo A, Holzwarth CW, Popović MA, Li H, Sun J, Bonifield T, Hollingsworth R, Kärtner FX, Smith HI, Stojanović V, Ram RJ. Nanophotonic integration in state-of-the-art cmos foundries. Opt. Express. 2011;19:2335–46.CrossRefGoogle Scholar
  40. 40.
    Biberman A, Preston K, Hendry G, Sherwood-droz N, Chan J, Levy JS, Lipson M, Bergman K. Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors. ACM J Emerg Technol Comput Syst. 2011;7(2):1305–15.CrossRefGoogle Scholar
  41. 41.
    Hendry G, Robinson E, Gleyzer V, Chan J, Carloni LP, Bliss N, Bergman K. Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors. J Parallel Distrib Comput. 2011;71:641–50.CrossRefGoogle Scholar
  42. 42.
    Chen C, Joshi A. Runtime management of laser power in silicon-photonic multibus noc architecture. IEEE J Sel Top Quantum Electron. 2013;19(2):338.Google Scholar
  43. 43.
    Zhou L, Kodi A. Probe: prediction-based optical bandwidth scaling for energy-efficient nocs. In: 2013 Seventh IEEE/ACM international symposium on networks on chip (NoCS), 2013. pp. 1–8.Google Scholar
  44. 44.
    Kodi A, Morris R. Design of a scalable nanophotonic interconnect for future multicores. In: The 5th ACM/IEEE symposium on architectures for networking and communications systems, ACM, 2009. pp. 113–22Google Scholar
  45. 45.
    Morris RW, Kodi AK. Power-efficient and high-performance multi-level hybrid nanophotonic interconnect for multicores. In: 4th ACM/IEEE international symposium on networks-on-chip (NoCS), 2010. pp. 207–14.Google Scholar
  46. 46.
    Bahirat S, Pasricha S. Uc-photon: a novel hybrid photonic network-on-chip for multiple use-case applications. In: 2010 11th International symposium on quality electronic design (ISQED), IEEE, 2010. pp. 721–9.Google Scholar
  47. 47.
    Xue J, Garg A, Ciftcioglu B, Hu J, Wang S, Savidis I, Jain M, Berman R, Liu P, Huang M, Wu H, Friedman E, Wicks G, Moore D. An intra-chip free-space optical interconnect. In: Proceedings of the 37th annual international symposium on Computer architecture, ISCA ’10, (New York, NY, USA), ACM, 2010. pp. 94–105.Google Scholar
  48. 48.
    Gratz P, Keckler SW. Realistic workload characterization and analysis for networks-on-chip design. In: The 4th workshop on chip multiprocessor memory systems and interconnects (CMP-MSI), 2010.Google Scholar
  49. 49.
    Tan MRT, Rosenberg P, Mathai S, Straznicky J, Kiyama L, Yeo JS, Mclaren M, Mack W, Mendoza P, Kuo HP. Photonic interconnects for computer applications. In: Communications and photonics conference and exhibition (ACP), 2009 Asia, 2009. pp. 1–2.Google Scholar
  50. 50.
    Prabhu S, Grot B, Gratz P, Hu J. Ocin tsim-DVFS aware simulator for NoCs. In: Proc. SAW. vol. 1, 2010.Google Scholar
  51. 51.
    Bienia C, Kumar S, Singh JP, Li K. The PARSEC benchmark suite: characterization and architectural implications. In: The 17th international conference on parallel architectures and compilation techniques (PACT), 2008.Google Scholar
  52. 52.
    Hestness J, Keckler S. Netrace: dependency-tracking traces for efficient network-on-chip experimentation. Tech. Rep., Technical Report TR-10-11, The University of Texas at Austin, Department of Computer Science,, 2010.
  53. 53.
    Kim H, Ghoshal P, Grot B, Gratz PV, Jimenez DA. Reducing network-on-chip energy consumption through spatial locality speculation. In: 5th ACM/IEEE international symposium on networks-on-chip (NoCS), 2011. pp. 233–40.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.HP LaboratoriesPalo AltoUSA
  2. 2.Texas A&M UniversityCollege StationUSA

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