Abstract
In the previous chapters, we discussed in detail many facets of micro-relay technology: from device fabrication and operation to scaling and energy implications. While the previous discussion aimed to demonstrate the viability of micro-relays as an underlying technology, the next two chapters will demonstrate how micro-relays can be integrated into the existing CMOS design infrastructure. As mentioned earlier, one of the unspoken criterion for a CMOS replacement technology is that it be compatible with the extensive existing infrastructure that has been built around CMOS technology [1]. This implied requirement is largely the reason behind choosing to explore the use of a four-terminal micro-relay first, since it shares functional similarities with an MOS transistor. In particular, we will show how micro-relays can implement many of the same functional circuits as used in CMOS at a lower energy cost while using the same simulation and design tool environments.
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Appendix: Micro-relay Verilog-A Model
Appendix: Micro-relay Verilog-A Model
The following text is an example of a micro-relay Verilog-A model, first used in [12], suitable for circuit simulation in either Spectre or HSPICE environments.
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Kam, H., Chen, F. (2015). Integrated Circuit Design with Micro-relays. In: Micro-Relay Technology for Energy-Efficient Integrated Circuits. Microsystems and Nanosystems, vol 1. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2128-7_6
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DOI: https://doi.org/10.1007/978-1-4939-2128-7_6
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