Electrical and Multiple Physics Simulation for Analog and Power WLCSP

  • Shichun Qu
  • Yong Liu


The electrical performance (such as electrical resistance, inductance, and capacitance) is a key factor for a WLCSP product. Many studies, such as the electrical performance of different devices, effect of assembly reflow process on electrical properties, and the resistance of a solder joint, have been done to improve a product’s electrical performance [1–3]. In recent years, the investigation for the electrical performance of a WLCSP has been paid more attention due to the wide applications of the WLCSP. The parasitic resistance, inductance, and capacitance (RLC) will impact the efficiency and switch speed of the WLCSP circuit. The electromigration issue of WLCSP, which is a multi-physics problem, becomes more critical due to the high current density in analog and power electronics. This chapter will introduce the electrical parasitic RLC simulation and electromigration simulation methods for WLCSP and wafer level interconnects.


Solder Joint Atomic Density Solder Bump Wafer Level Wire Bonding Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Liu, Y.: Power electronic packaging: Design, assembly process, reliability and modeling. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  2. 2.
    Sasagawa, K., Hasegawa, M., Saka, M., Abe, H.: Prediction of electromigration failure in passivated polycrystalline line. J. Appl. Phys. 91(11), 9005–9014 (2002)CrossRefGoogle Scholar
  3. 3.
    Sukharev, V., Zschech, E.: A model for electromigration-induced degradation mechanisms in dual-inlaid copper interconnects: Effect of interface bonding strength. J. Appl. Phys. 96(11), 6337–6343 (2004)CrossRefGoogle Scholar
  4. 4.
    Tan, C.M., Hou, Y.J., Li, W.: Revisit to the finite element modeling of electromigration for narrow interconnects. J. Appl. Phys. 102(3), 1–7 (2007)CrossRefGoogle Scholar
  5. 5.
    Tan, C.M., Roy, A.: Investigation of the effect of temperature and stress gradients on accelerated EM test for Cu narrow interconnects. Thin Solid Films 504(1–2), 288–293 (2006)CrossRefGoogle Scholar
  6. 6.
    Tu, K.N.: Recent advances on electromigration in very-large-scale-integration of interconnects. J. Appl. Phys. 94(9), 5451–5473 (2003)CrossRefGoogle Scholar
  7. 7.
    Liu, Y., Zhang, Y.X., Liang, L.H.: Prediction of electromigration induced voids and time to failure for solder joint of a wafer level chip scale package. IEEE Trans. Component Packag. Technol. 33(3), 544–552 (2010)CrossRefGoogle Scholar
  8. 8.
    Dalleau, D., Weide-Zaage, K., Danto, Y.: Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures. Microelectron. Reliab. 43(9–11), 1821–1826 (2003)CrossRefGoogle Scholar
  9. 9.
    Wilson, S.R., et al.: Handbook of multilevel metallization for integrated circuits: Materials, technology, and applications, p. 116. Noyes, Park Redge, NJ (1993)Google Scholar
  10. 10.
    Zhao, J.H., Ryan, T., et al.: Measurement of elastic modulus, Poisson ratio, and coefficient of thermal expansion of on-wafer submicron films. J. Appl. Phys. 85(9), 6421–6424 (1999)CrossRefGoogle Scholar
  11. 11.
    Sharpe, William N., Yuan, Jr. B., Vaidyanathan, R.: Measurement of Young’s modulus, Poisson’s ratio, and tensile strength of polysilicon. In: Proc 8th IEEE International Workshop on Microelectromechanical Systems, Nagoya, Japan. (1997)Google Scholar
  12. 12.
    JEDEC, JEP119A: A Procedure for performing SWEAT. (2003)Google Scholar
  13. 13.
    Ni, J., Liu, Y., Hao, J., Maniatty, A., OConnell, B.: Modeling microstructure effects on electromigration in lead-free solder joints. ECTC64, Orlando, FL (2014)Google Scholar
  14. 14.
    Liu, Y., Irving, S., Luk, T., et al.: 3D modeling of electromigration combined with thermal-mechanical effect for IC device and package. EuroSime 2007Google Scholar
  15. 15.
    Liu, Y.: Finite element modeling of electromigration in solder bumps of a package system. Professional Development Course, EPTC, Singapore (2008)Google Scholar
  16. 16.
    Yang, S., Tian, Y., Wang, C., Huang,T.: Modeling thermal fatigue in anisotropic Sn-Ag-Cu/Cu solder joints. International Conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), (2009)Google Scholar
  17. 17.
    Subramanian, K.N., Lee, J.G.: Effect of anisotropy of tin on thermomechanical behavior of solder joints. J. Mater. Sci. Mater. Electron. 15(4), 235–240 (2004)CrossRefGoogle Scholar
  18. 18.
    Gee, S., Kelkar, N., Huang,J., Tu, K.: Lead-free and PbSn Bump Electrmigration Testing. In: Proceedings of IPACK2005, IPACK2005-73417, July 17–22Google Scholar
  19. 19.
    Wang, Q., et al.: Experimental determination and modification of the Anand model constants for 95.5Sn4.0Ag0.5Cu. Eurosime 2007, London, UK, April, (2007)Google Scholar
  20. 20.
    Zhao, J., Su, P., Ding, M., Chopin, S., Ho, P.S.: Microstructure-based stress modeling of tin whisker growth. IEEE Trans. Electron. Packag. Manuf. 29(4), 265–273 (2006)CrossRefGoogle Scholar
  21. 21.
    Puttlitz, K. J., Stalter, K. A: Handbook of Lead-free solder technology for microelectronic assemblies. pp. 920–926. (2004)Google Scholar
  22. 22.
    Huntington, H.B.: Effect of driving forces on atom motion”. Thin Solid Films 25(2), 265–280 (1975)MathSciNetCrossRefGoogle Scholar
  23. 23.
    Huang, F.H., Huntington, H.B.: Diffusion of Sb124, Cd109, Sn113, and Zn65 in tin. Phys. Rev. B 9(4), 1479–1488 (1974)CrossRefGoogle Scholar
  24. 24.
    Lu, M., Shih, D., Lauro, P., Goldsmith, C., Henderson, D.W.: Effect of Sn grain orientation on electromigration degradation in high Sn-based Ph-free solders”. Appl. Phys. Lett. 92, 211909 (2008)CrossRefGoogle Scholar
  25. 25.
    Xu, J.: Study on lead-free solder joint reliability based on grain orientation. Acta Metallurgica Sinica 48(9), 1042–1048 (2012)Google Scholar
  26. 26.
    Park, S., Dhakal, R., Gao, J.: Three-dimensional finite element analysis of multiple-grained lead-free solder interconnects. J. Electron Mater. 37(8), 1139–1147 (2008)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Shichun Qu
    • 1
  • Yong Liu
    • 2
  1. 1.Fairchild SemiconductorSan JoseUSA
  2. 2.Fairchild SemiconductorSouth PortlandUSA

Personalised recommendations