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Stackable Wafer-Level Analog Chip-Scale Package

  • Shichun Qu
  • Yong Liu
Chapter
  • 2.1k Downloads

Abstract

Stacking is a trend that has brought and still brings excitements to the semiconductor packaging societies. While the main driving force for the stacked package has been high level of integration and smaller package footprint, improvement of electrical performance due to the shortened path of signal transmission and power distribution is also frequently referred. Though it is relatively rare, improvement of overall thermal performance is occasionally mentioned as well. More frequently, heat dissipation is one of the mostly concerned areas for the stacked package. Cost of manufacturing the 3D structure seems to be the main hurdle for wider adoptions of the more aggressive 3D package concepts.

Keywords

Solder Bump Wire Bond Wafer Bonding Flip Chip Bosch Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Shichun Qu
    • 1
  • Yong Liu
    • 2
  1. 1.Fairchild SemiconductorSan JoseUSA
  2. 2.Fairchild SemiconductorSouth PortlandUSA

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