Abstract
The concept of fan-out is hardly new for semiconductor packaging. Ever since the early days of semiconductor industry, fan-out scheme that expands the tight lead pitch on semiconductor to coarse lead pitch on package is the dominant form in all chip packages, for example, leadframe package fan-out from chip to leads via bonding wires and flip chip package fan-out from chip to BGA via inner metal layers in the substrate (Fig. 3.1a, b).
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Notes
- 1.
Redistributed chip package (RCP) is a proprietary packaging technology developed by Freescale Semiconductor.
- 2.
Embedded wafer-level ball-grid array is a proprietary packaging technology developed by Infineon Technologies AG.
References
Keser, B., Amrine, C., Duong, T., et al.: Advanced packaging: the redistributed chip package. IEEE Trans. Adv. Packaging 31(1), 39–43 (2008)
Ramanathan, L.N., Leal, G.R., Mitchell, D.G., Yeung, B.H.: Method for controlling warpage in redistributed chip package, United States Patent US7950144B2, May (2011)
Sharma, G., Kumar, A., Rao, V.S., et al.: Solutions strategies for die shift problem in wafer level compression molding. IEEE Trans. Compon. Packaging Manuf. Technol. 1(4), 502–509 (2011)
Hasegawa, T., Abe, H., Ikeuchi, T.: Wafer level compression molding compounds. 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA (2012)
Itabashi, T., Dielectric materials evolve to meet the challenges of wafer-level packaging. Solid State Technol., November 01 (2010)
Iwashita, K., Hattori, T., Minegishi, T., Ando, S., Toyokawa, F., Ueda, M.: Study of polybenzoxazole precursors for low temperature curing. J. Photopolym. Sci. Technol. 19(2), 281–282 (2006)
Hirano, T., Yamamoto, K., Imamura, K.: Application for WLP at positive working photosensitive polybenzoxazole. J. Photopolym. Sci. Technol. 19(2), 281–282 (2006)
Fan, X.J., Varia, B., Han, Q.: Design and optimization of thermo-mechanical reliability in wafer level packaging. Microelectron. Reliab. 50, 536–546 (2010)
Olson, T.L., Scanlan, C.M.: Adaptive patterning for panelized packaging, United States Patent Application Publication, No. US2013/0167102 A1
Oh, J.H., Lee, S.J., Kim, J.G.: Semiconductor device and method of forming FO-WLCSP having conductive layers and conductive vias separated by polymer layers, US Patent 8,343,810B2, Jan. 1 (2013)
Braun, T., Becker, K.-F., Voges, S., et al.: From wafer level to panel level mold embedding, 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV (2013)
Liu, H.W., Liu, Y.W., Ji, J., et al.: Warpage characterization of panel fan-out (P-FO) package, 64th Electronic Components and Technology Conference (ECTC), Orlando, FL (2014)
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Qu, S., Liu, Y. (2015). Fan-Out Wafer-Level Chip-Scale Package. In: Wafer-Level Chip-Scale Packaging. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-1556-9_3
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DOI: https://doi.org/10.1007/978-1-4939-1556-9_3
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