WLCSP Typical Reliability and Test

  • Shichun Qu
  • Yong Liu


WLCSP is one of the fastest growing segments in semiconductor packaging industry due to the rapid advances in integrated circuit (IC) fabrication, small form factor, and low cost. This technology results in a lower cost per die (vs. traditional wirebond) when the die count per wafer is high. As the number of I/O per die increases (and thus the die size and the distance to neutral point increases), the WLCSP may not achieve prescribed solder joint reliability requirements; the metal stack (UBM and the Al pad), passivation, or polyimide may also appear to fail, especially when the WLCSP is mounted on the PCB. The board level reliability is a big concern for both analog and power WLCSP packaging. This chapter will discuss the WLCSP typical reliability test.


Solder Joint Solder Ball Solder Bump Drop Test Cohesive Zone Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Liu, Y.: Power electronic packaging: Design, assembly process, reliability and modeling. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  2. 2.
    Chai, T. C., Yu, D. Q., Lau, J., et al.: Angled high strain rate shear testing for SnAgCu solder balls. In: Proceedings of 58th Electronic Components and Technology Conference, pp. 623–628. (2008)Google Scholar
  3. 3.
    Zhang,Y., Xu, Y., Liu,Y., Schoenberg, A.: The experimental and numerical investigation on shear behavior of solder ball in a Wafer Level Chip Scale Package, ECTC 60, (2010)Google Scholar
  4. 4.
    Dugdale, D.S.: Yielding of steel sheets containing slits. J. Mech. Phys. Solids 8, 100–108 (1960)CrossRefGoogle Scholar
  5. 5.
    Barenblatt, G.I.: The mathematical theory of equilibrium of crack in brittle fracture. Adv. Appl. Mech. 7, 55–129 (1962)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Needleman, A.: A continuum model for void nucleation by inclusion debonding. ASME J. Appl. Mech. 54, 525–531 (1987)CrossRefzbMATHGoogle Scholar
  7. 7.
    Tvergaard, V., Hutchinson, J.W.: The influence of plasticity on mixed mode interface toughness. J. Mech. Phys. Solids 41, 1119–1135 (1993)CrossRefzbMATHGoogle Scholar
  8. 8.
    Tvergaard, V., Hutchinson, J.W.: On the toughness of ductile adhesive joints. J. Mech. Phys. Solids 44, 789–800 (1996)CrossRefGoogle Scholar
  9. 9.
    Liu, Y., Qian, Q., Qu, S., Martin, S., Jeon, O.: Investigation of the assembly reflow process and PCB design on the reliability of WLCSP. ECTC62. (2012).Google Scholar
  10. 10.
    Liu, Y., Qian, Q., Kim, J., Martin, S.: Board level drop impact simulation and test for development of wafer level chip scale package. ECTC 60. (2010)Google Scholar
  11. 11.
    Dhiman, H.S., Fan, X.J., Zhou, T.: JEDEC board drop test simulation for wafer level packages (WLPs). ECTC59. (2009)Google Scholar
  12. 12.
    Liu, Y., Qian, Q., Ring, M., et al.: Modeling for critical design and performance of wafer level chip scale package. ECTC62. (2012)Google Scholar
  13. 13.
    Liu, Y.M., Liu, Y.: Prediction of board level performance of WLCSP. ECTC63. (2013)Google Scholar
  14. 14.
    Liu, Y.M., Liu, Y., Qu, S.: Bump geometric deviation on the reliability of BOR WLCSP. ECTC 64. (2014)Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Shichun Qu
    • 1
  • Yong Liu
    • 2
  1. 1.Fairchild SemiconductorSan JoseUSA
  2. 2.Fairchild SemiconductorSouth PortlandUSA

Personalised recommendations