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Demand and Challenges for Wafer-Level Chip-Scale Analog and Power Packaging

  • Shichun Qu
  • Yong Liu
Chapter
  • 2.2k Downloads

Abstract

A review of recent advances in analog and power wafer-level chip-scale packaging (WLCSP) is presented based on the development and market demand in semiconductor industry. This chapter covers in more detail how advances in both the analog and power advanced wafer-level package fan-in/fan-out design and 3D integration have co-enabled significant advances in analog and power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in techniques of analog, power switches, and passives can drive continued enhancements in usability, efficiency, reliability, and overall cost of analog and power semiconductor solutions. Challenges of die shrinkage in both wafer-level analog and power semiconductor packaging in next-generation design are presented and discussed.

Keywords

Solder Ball Fine Pitch Power Semiconductor Current Carry Capability Good Electrical Performance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Shichun Qu
    • 1
  • Yong Liu
    • 2
  1. 1.Fairchild SemiconductorSan JoseUSA
  2. 2.Fairchild SemiconductorSouth PortlandUSA

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