Demand and Challenges for Wafer-Level Chip-Scale Analog and Power Packaging

  • Shichun Qu
  • Yong Liu


A review of recent advances in analog and power wafer-level chip-scale packaging (WLCSP) is presented based on the development and market demand in semiconductor industry. This chapter covers in more detail how advances in both the analog and power advanced wafer-level package fan-in/fan-out design and 3D integration have co-enabled significant advances in analog and power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in techniques of analog, power switches, and passives can drive continued enhancements in usability, efficiency, reliability, and overall cost of analog and power semiconductor solutions. Challenges of die shrinkage in both wafer-level analog and power semiconductor packaging in next-generation design are presented and discussed.


Solder Ball Fine Pitch Power Semiconductor Current Carry Capability Good Electrical Performance 
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  1. 1.
    Liu, Y.: Reliability of power electronic packaging. International Workshop on Wide-Band-Gap Power Electronics, Hsingchu, April (2013)Google Scholar
  2. 2.
    Liu, Y.: Power electronics packaging. Seminar on Micro/Nanoelectronics System Integration and Reliability, Delft, April (2014)Google Scholar
  3. 3.
    Kinzer, D.: (Keynote) Trends in analog and power packaging. EuroSimE, Delft, April (2009)Google Scholar
  4. 4.
    Liu, Y., Kinzer, D.: (Keynote) Challenges of power electronic packaging and modeling. EuroSimE, Linz, April (2011)Google Scholar
  5. 5.
    Liu, Y.: (Keynote) Trends of analog and power electronic packaging development. ICEPT, Guilin, August, (2012)Google Scholar
  6. 6.
    Hao, J., Liu, Y., Hunt, J., Tessier, T., et al.: Demand for wafer-level chip-scale packages accelerates, 3D Packages, No. 22, Feb (2012)Google Scholar
  7. 7.
    Yannou, J-M.: Market dynamics impact WLCSP adoption, 3D Packages, No. 22, Feb (2012)Google Scholar
  8. 8.
    Shimaamoto, H.: Technical trend of 3D chip stacked MCP/SIP. ECTC57 Workshop (2007)Google Scholar
  9. 9.
    Orii, Y., Nishio, T.: Ultra thin PoP technologies using 50 μm pitch flip chip C4 interconnection. ECTC57 Workshop (2007)Google Scholar
  10. 10.
    Meyer-Berg, G.: (Keynote) Future packaging trends, Eurosime 2008, GermanyGoogle Scholar
  11. 11.
    Vardaman, E.J.: Trends in 3D packaging, ECTC 58 short course (2008)Google Scholar
  12. 12.
    Fontanclli, A.: System-in-package technology: opportunities and challenges. 9th International Symposium on Quality Electronic Design, pp. 589–593 (2008)Google Scholar
  13. 13.
    Meyer, T., Ofner, G., Bradl, S., et al.: Embedded wafer level ball grid array (eWLB), EPTC 2008, pp 994–998Google Scholar
  14. 14.
    Lee, F.: Survey of trends for integrated point-of-load converters, APEC 2009, Washington DC (2009)Google Scholar
  15. 15.
    Hashimoto, T., et al.: System in package with mounted capacitor for reduced parasitic inductance in voltage regulators. Proceedings of the 20th International Symposium on Power Semiconductor Devices and ICs, 2008, Orlando, FL, May, 2008, pp. 315–318Google Scholar
  16. 16.
    Liu, S., Liu, Y.: Modeling and Simulation for Microelectronic Packaging Assembly. Wiley, Singapore (2011)CrossRefGoogle Scholar
  17. 17.
    Fan, X.J.: (Keynote) Wafer level packaging: Fan-in, fan-out and 3D integration, ICEPT, Guilin, August (2012)Google Scholar
  18. 18.
    Liu, Y.: Power electronic packaging: design, assembly process, reliability and modeling. Springer, New York (2012)CrossRefGoogle Scholar
  19. 19.
    Wang, Q., Ho, I., Li, M.: Enhanced electrical and thermal properties of trench metal-oxide-semiconductor field-effect transistor built on copper substrate. IEEE Electron Device Lett. 30, 61–63 (2009)CrossRefGoogle Scholar
  20. 20.
    Zhao, M., Huang, Z.: Rena, Design of on-chip microchannel fluidic cooling structure, ECTC 2007, Reno, NV, pp. 2017–2023 (2007)Google Scholar
  21. 21.
    Liu, Y.: Analog and power packaging, professional short course, ECTC 62, San Diego (2012)Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Shichun Qu
    • 1
  • Yong Liu
    • 2
  1. 1.Fairchild SemiconductorSan JoseUSA
  2. 2.Fairchild SemiconductorSouth PortlandUSA

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