Scheduling Basic Blocks

  • Alex Aiken
  • Utpal Banerjee
  • Arun Kejariwal
  • Alexandru Nicolau
Chapter

Abstract

A basic block in a program is a sequence of consecutive operations, such that control flow enters at the beginning and leaves at the end without internal branches. While basic block scheduling is the simplest non-trivial instruction scheduling problem, it is also the most fundamental and widely used in both software and hardware implementations of instruction scheduling. This chapter introduces basic terminology used in all subsequent chapters and covers a number of different approaches to basic block scheduling.

Keywords

Compaction Dispatch 

Bibliography

  1. [Age76]
    T. Agerwala. Microprogram optimization: A survey. IEEE Transactions on Computers, C-25:962–973, October 1976.Google Scholar
  2. [AM88]
    V. H. Allan and R. A. Mueller. Compaction with general synchronous timing. IEEE Transactions on Software Engineering, 14(5):595–599, 1988.CrossRefGoogle Scholar
  3. [AR76]
    A. K. Agerwala and T. G. Rauscher. Foundations of Microprogramming Architecture, Software, and Applications. Academic Press, New York, NY, 1976.Google Scholar
  4. [Bak74]
    K. R. Baker. Introduction to sequencing and scheduling. John Wiley and Sons, New York, NY, 1974.Google Scholar
  5. [Ban76]
    U. Banerjee. Data dependence in ordinary programs. Master’s thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, November 1976. Report No. 76–837.Google Scholar
  6. [Ban97]
    U. Banerjee. Dependence Analysis. Kluwer Academic Publishers, Boston, MA, 1997.MATHGoogle Scholar
  7. [Ban11a]
    U. Banerjee. Basic block parallelization. In D. Padua, editor, Encyclopedia of Parallel Computing, pages 1450–1458. Springer, 2011.Google Scholar
  8. [Bar78]
    G. E. Barnes. Comments on the identification of maximal parallelism in straight-line microprograms. IEEE Transactions on Computers, C-27(3):286–287, March 1978.Google Scholar
  9. [BCS96]
    S. J. Beaty, S. Colcord, and P. H. Sweany. Using genetic algorithms to fine-tune instruction-scheduling heuristics. In Proceedings of the 2nd International Conference on Massively Parallel Computing Systems (MPCS’96), Ischia, Italy, May 1996.Google Scholar
  10. [Bea91]
    S. J. Beaty. Genetic algorithms and instruction scheduling. In Proceedings of the 24th International Symposium of Microarchitecture MICRO-24, pages 206–211, 1991.Google Scholar
  11. [Bea92]
    S. J. Beaty. Lookahead scheduling. In Proceedings of the 25th Annual International Symposium on Microarchitecture, pages 256–259, 1992.Google Scholar
  12. [BR91]
    D. Bernstein and M. Rodeh. Global instruction scheduling for superscalar machines. In Proceedings of the SIGPLAN ’91 Conference on Programming Language Design and Implementation, pages 241–255, 1991.Google Scholar
  13. [BTT99]
    S. Bharitkar, K. Tsuchiya, and Y. Takefuji. Microcode optimization with neural networks. IEEE Transactions on Neural Networks, 10(3):698–703, May 1999.Google Scholar
  14. [BWJ90]
    S. Beaty, D. Whitley, and G. Johnson. Motivation and framework for using genetic algorithms for microcode compaction. In Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and microarchitecture, pages 117–124, Orlando, FL, 1990.Google Scholar
  15. [CG72]
    E. Coffman and R. Graham. Optimal scheduling for two processor systems. Acta Informatica, 1(3):200–213, 1972.MathSciNetCrossRefMATHGoogle Scholar
  16. [CMM67]
    R. W. Conway, W. L. Maxwell, and L. W. Miller. Theory of scheduling. Addison-Wesley, Reading, MA, 1967.MATHGoogle Scholar
  17. [Cof76]
    E. Coffman, Jr. Computer and job-shop scheduling theory. John Wiley and Sons, New York, NY, 1976.MATHGoogle Scholar
  18. [CSS98]
    K. Cooper, P. Schielke, and D. Subramanian. An experimental evaluation of list scheduling. Technical Report 98–326, Rice University, September 1998.Google Scholar
  19. [Das77]
    S. Dasgupta. Parallelism in loop-free microprograms. In Information Processing ’77, North-Holland, pages 745–750, 1977.Google Scholar
  20. [DT76]
    S. Dasgupta and John Tartar. The identification of maximal parallelism in straight-line microprograms. IEEE Transactions on Computers, C-25(10):986–992, October 1976.Google Scholar
  21. [FGL94]
    S. M. Freudenberger, T. R. Gross, and P. G. Lowney. Avoidance and suppression of compensation code in a trace scheduling compiler. ACM Transactions on Programming Languages and Systems, 16(4):1156–1214, July 1994.Google Scholar
  22. [Fis79]
    J. A. Fisher. The Optimization of Horizontal Microcode Within and Beyond Basic Blocks: An Application of Processor Scheduling Beyond Basic Blocks. PhD thesis, New York University, 1979.Google Scholar
  23. [Fis81a]
    J. A. Fisher. Microcode compaction: Looking backward and looking forward. In Proceedings of the National Computer Conference, pages 95–102, Chicago, IL, July 1981.Google Scholar
  24. [Fis81b]
    J. A. Fisher. Trace Scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478–490, July 1981.Google Scholar
  25. [FR72]
    C. C. Foster and E. M. Riseman. Percolation of code to enhance parallel dispatching and execution. IEEE Transactions on Computers, C-21(12):1411–1415, December 1972.Google Scholar
  26. [Gon77]
    M. J. Gonzalez. Deterministic processor scheduling. ACM Computing Surveys, 9(3):173–204, September 1977.Google Scholar
  27. [Har87]
    M. Harris. Extending microcode compaction for real architectures. In Proceedings of the 20th Annual Workshop on Microprogramming, pages 40–53, Colorado Springs, CO, 1987.Google Scholar
  28. [Hu61]
    T. C. Hu. Parallel sequencing and assembly line problems. Operations Research, 9(6):841–848, 1961.MathSciNetCrossRefGoogle Scholar
  29. [Hus70]
    S. S. Husson. Microprogramming: Principles and Practices. Prentice-Hall, Englewood Cliff, NJ, 1970.Google Scholar
  30. [IKI83]
    S. Isoda, Y. Kobayaski, and T. Ishida. Global compaction of horizontal microprograms based on generalized data dependency graph. IEEE Transactions on Computers, C-32(10):922–933, October 1983.Google Scholar
  31. [JD74]
    L. W. Jackson and S. Dasgupta. The identification of parallel microoperations. Information Processing Letters, 2:180–184, March 1974.Google Scholar
  32. [KT79]
    J. Kim and C. J. Tan. Register assignment algorithms for optimizing micro-code compliers - Part I. Technical Report RC 4633 (# 20545), IBM T. J. Watson Research Center, May 1979.Google Scholar
  33. [LDSM80]
    D. Landskov, S. Davidson, B.D. Shriver, and P.W. Mallett. Local microcode compaction techniques. ACM Computing Surveys, 12(3):261294, September 1980.Google Scholar
  34. [MDO84]
    R. A. Mueller, M. R. Duda, and S. M. O’Haire. A survey of resource allocation methods in optimizing microcode compilers. In Proceedings of the 17th Annual Workshop on Microprogramming, pages 285–295, 1984.Google Scholar
  35. [MPF82]
    M. Mezzalama, P. Prinetto, and G. Filippi. Microcode compaction via microblock definition. In Proceedings of the 15th Annual Workshop on Microprogramming, pages 134–142, Palo Alto, CA, 1982.Google Scholar
  36. [PK89]
    P. Paulin and J. Knight. Force-directed scheduling for the behavioral synthesis of ASIC’s. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(6):661–679, 1989.CrossRefGoogle Scholar
  37. [Poe80]
    M. D. Poe. Heuristics for the global optimization of microprograms. In Proceedings of the 13th Annual Workshop on Microprogramming, pages 13–22, Springs, CO, 1980.Google Scholar
  38. [RCG72]
    C. V. Ramamoorthy, K. M. Chandy, and M. J. Gonzalez. Optimal scheduling strategies in a multiprocessor system. IEEE Transactions on Computers, C-21(2):137–146, February 1972.Google Scholar
  39. [RF72]
    E. M. Riseman and C. C. Foster. The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers, C-21(12):1405–1411, December 1972.Google Scholar
  40. [SB92]
    P. H. Sweany and S. J. Beaty. Dominator-path scheduling: A global scheduling method. In Proceedings of the 25th International Symposium of Microarchitecture, pages 260–263, 1992.Google Scholar
  41. [Sch00]
    P. J. Schielke. Stochastic Instruction Scheduling. PhD thesis, Dept. of Computer Science, Rice University, May 2000.Google Scholar
  42. [SD85]
    B. Su and S. Ding. Some experiments in global microcode compaction. In Proceedings of the 18th Annual Workshop on Microprogramming, pages 175–180, Pacific Grove, CA, 1985.Google Scholar
  43. [SWX88]
    B. Su, J. Wang, and J. Xia. Global microcode compaction under timing constraints. In Proceedings of the 21st Annual Workshop on Microprogramming and microarchitecture, pages 116–118, San Diego, CA, 1988.Google Scholar
  44. [TF70]
    G.S. Tjaden and M.J. Flynn. Detection and parallel execution of independent instructions. IEEE Transactions on Computers, C-19(10):889–895, 1970.CrossRefGoogle Scholar
  45. [TTT81]
    M. Tokoro, E. Tamura, and T. Takizuka. Optimization of microprograms. IEEE Transactions on Computers, 30(7):491–504, 1981.CrossRefGoogle Scholar
  46. [TTTT77]
    M. Tokoro, E. Tamura, K. Takase, and K. Tamaru. An approach to microprogram optimization considering resource occupancy and instruction formats. In Proceedings of the 10th Workshop on Microprogramming, pages 92–108, October 1977.Google Scholar
  47. [TTTY78]
    M. Tokoro, T. Takizuka, E. Tamura, and I. Yamaura. A technique of global optimization of microprograms. In Proceedings of the 11th Annual Workshop on Microprogramming, pages 41–50, Pacific Grove, CA, 1978.Google Scholar
  48. [Woo78]
    G. Wood. On the packing of micro-operations into micro-instruction words. In Proceedings of the 11th Annual Workshop on Microprogramming, pages 51–55, Pacific Grove, CA, 1978.Google Scholar
  49. [Woo79]
    G. Wood. Global optimization of microprograms through modular control constructs. In Proceedings of the 12th Workshop on Microprogramming, pages 1–6, 1979.Google Scholar

Copyright information

© Springer-Verlag US 2016

Authors and Affiliations

  • Alex Aiken
    • 1
  • Utpal Banerjee
    • 2
  • Arun Kejariwal
    • 3
  • Alexandru Nicolau
    • 4
  1. 1.Department of Computer ScienceStanford UniversityStanfordUSA
  2. 2.Department of Computer ScienceUniversity of California at IrvineIrvineUSA
  3. 3.MZ Inc.Palo AltoUSA
  4. 4.Center for Embedded Computer SystemsUniversity of California at IrvineIrvineUSA

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