Design of asynchronous circuits

  • D. Lewin
  • D. Protheroe

Abstract

In the last two chapters we have considered synchronous (clocked) sequential circuits; asynchronous circuits are in principle very similar, but special design techniques must be employed to overcome the problems brought about by the absence of any timing pulses, that is, the absence of a common clock signal. These problems arise mainly as a result of the finite switching time, or propagation delay, of the basic logic modules. In synchronous systems, the clock pulses ensure that the output and input variables are sampled when the circuits have reached a steady state after the delays have settled out. In the absence of any timing pulses, we have to consider two possible conditions for an asynchronous circuit — the stable and unstable states.

Keywords

Resis Tate Pyramid Lewin 

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References and Bibliography

  1. 1.
    Seitz, C. (1980) Systems timing, in Introduction to VLSI Systems (eds C. Mead and L. Conway), Chapter 7, Addison-Wesley.Google Scholar
  2. 2.
    Huffman, D.A. (1954) The synthesis of sequential switching circuits. J. Franklin Inst., 257, 161–90, 257–303.Google Scholar
  3. 3.
    Maley, G.A. and Earle, J. (1963) The Logic Design of Transistor Digital Computers,Prentice-Hall.Google Scholar
  4. 4.
    Huffman, D.A. (1957) The design and use of hazard-free switching networks. J. Ass. Comput. Mach., 4, 47–62.MathSciNetCrossRefGoogle Scholar
  5. 5.
    Marcus, M. (1975) Switching Circuits for Engineers,2nd edn, Prentice-Hall.Google Scholar
  6. 6.
    Liu, C.N. (1963) A state-variable assignment method for asynchronous sequential switching circuits. J. Ass. Comput. Mach., 10, 209–16.CrossRefMATHGoogle Scholar
  7. 7.
    Tracey, J.H. (1966) Internal state assignment for asynchronous sequential machines. IEEE Trans. Electron. Comput., EC15, 551–60.Google Scholar
  8. 8.
    Smith, R.J. et al. (1968) Automation in the design of asynchronous sequential circuits. IFIPS SJCC, 32, 55–60.Google Scholar
  9. 9.
    Smith, R.J. (1974) Generation of internal state assignment for large asynchronous sequential machines. IEEE Trans. Comput., C23, 924–32.CrossRefMATHGoogle Scholar
  10. 10.
    Ungar, S.H. (1969) Asynchronous Sequential Switching Circuits,Wiley.Google Scholar
  11. 11.
    Hollaar, L.A. (1982) Direct implementation of asynchronous control units. IEEE Trans. Computers, C31, 1133–41.CrossRefGoogle Scholar
  12. 12.
    Ungar, S.H. (1959) Hazards and delays in asynchronous sequential switching circuits. IRE Trans. Circuit Theory, CT6, 12–25.Google Scholar
  13. 13.
    McLuskey, E.J. (1962) Transients in combinational logic circuits, in Redundancy Techniques for Computing Systems (eds R.H. Wilcox and W.C. Mann ), Spartan Book Co.Google Scholar
  14. 14.
    Eichelberger, E.B. (1965) Hazard detection in combinational and sequential switching circuits. IBM J. Res. Dey., 9, 90–9.CrossRefMATHGoogle Scholar
  15. 15.
    Armstrong, D.B., Friedman, A.D. and Menon, P.R. (1968) Realisation of asynchronous sequential circuits without inserted delay elements. IEEE Trans. Computers, C17, 129–34.CrossRefGoogle Scholar
  16. 16.
    Sholl, H.A. and Yang, S.C. (1975) Design of asynchronous sequential networks using read only memory. IEEE Trans. Computers, C24, 195–206.MathSciNetCrossRefMATHGoogle Scholar
  17. 17.
    Keller, R.M. (1974) Towards a theory of universal speed-independent modules. IEEE Trans. Comp., C-23 (1), 21–33.Google Scholar
  18. 18.
    Peterson, J.L. (1981) Petri Net Theory and the Modeling of Systems,Prentice-Hall.Google Scholar
  19. 19.
    Howard, B.V. (1975) Parallel computation schemata and their hardware implementation. Digital Processes, 1, 183–206.MATHGoogle Scholar
  20. 20.
    Protheroe, D. (1990) Design automation based upon a distributed self-timed architecture, in Proc. IEE UK IT Conf. 1990, IEE Publ. 316, 394–403.Google Scholar
  21. 21.
    Karp, R.M. and Miller, R.E. (1969) Parallel program schemata. J. Comput and Syst. Sci., 3, 147–95.MathSciNetCrossRefMATHGoogle Scholar
  22. 22.
    Vallette, R. and Diaz, M. (1978) Top-down formal specification and verification of parallel control systems. Digital Processes, 4, 181–99.MathSciNetGoogle Scholar
  23. 23.
    Heath, F.G., Foulk, P.W. and Li, D.Y. (1984) Analysis and restructuring of concurrent systems using Prolog. IEE Proc. Pt E, 131 (5), 169–76.Google Scholar

Copyright information

© D. Lewin and D. Protheroe 1992

Authors and Affiliations

  • D. Lewin
    • 1
  • D. Protheroe
    • 2
  1. 1.University of SheffieldUK
  2. 2.South Bank UniversityLondonUK

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