Design of asynchronous circuits

  • D. Lewin
  • D. Protheroe


In the last two chapters we have considered synchronous (clocked) sequential circuits; asynchronous circuits are in principle very similar, but special design techniques must be employed to overcome the problems brought about by the absence of any timing pulses, that is, the absence of a common clock signal. These problems arise mainly as a result of the finite switching time, or propagation delay, of the basic logic modules. In synchronous systems, the clock pulses ensure that the output and input variables are sampled when the circuits have reached a steady state after the delays have settled out. In the absence of any timing pulses, we have to consider two possible conditions for an asynchronous circuit — the stable and unstable states.


Unstable State State Diagram Logic Circuit Secondary Variable Input Place 
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Copyright information

© D. Lewin and D. Protheroe 1992

Authors and Affiliations

  • D. Lewin
    • 1
  • D. Protheroe
    • 2
  1. 1.University of SheffieldUK
  2. 2.South Bank UniversityLondonUK

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