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EPROM/Flash Explorer

  • James R. Strickland
Chapter

Abstract

Every time you load a sketch to the Cestino, the software on your host computer compiles the sketch into instructions and uploads it into the Cestino's flash memory. You know all this.

Keywords

Data Line Floating Gate Command Sequence Address Line JEDEC Standard 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© James R. Strickland 2016

Authors and Affiliations

  • James R. Strickland
    • 1
  1. 1.Highlands RanchUSA

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