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Yield Evaluation of a Soft-Configurable WSI Switch Network

  • M. Blatt

Abstract

A network of fault tolerant switches is used to implement a pipelined memory system, and some measures of its fault tolerance presented. Simulations directly from the circuit layout provide yield estimates for each circuit piece. Such simulations predict that random point defects will cause less than 1% of the 1266-transistor switches to fail. Yield estimates for each circuit piece are used as inputs to a yield model to evaluate the fault tolerance of the entire design.

Keywords

Balance Load Fault Tolerance Memory Block Switch Node Switch Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. Katevenis, M.G.H., 1987, Fast Switching and Fair Control of Congested Flow in Broad-Band Networks, IEEE Journal on Selected Areas in Communications, 5:1315.Google Scholar
  2. Katevenis, M.G.H. and Blatt, M.G., 1985, Switch Design for Soft-Configurable WSI Systems, in “1985 Chapel Hill Conference on VLSI”, pp. 197-219.Google Scholar
  3. Lukaszek, W., 1988, private communication.Google Scholar
  4. Walker, D.M.H., 1986, Yield simulation for integrated circuits, PhD Thesis, Carnegie Mellon, CMU-CS-86-143.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • M. Blatt
    • 1
  1. 1.Center for Integrated SystemsStanford UniversityStanfordUSA

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