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A Unified Approach to Yield Analysis of Defect Tolerant Circuits

  • Z. Koren
  • I. Koren

Abstract

The dependence of the yield of defect tolerant VLSI circuits on the size of defect clusters (relative to the chip size) has been recently recognized. Consequently, models for yield analysis have been proposed for “large area clustering” and “small area clustering”. By adding a new parameter, the block size, to the existing parameters of the defect distribution we unify the analysis of the existing models and at the same time add a whole range of “medium size clustering” models, thus increasing the flexibility in choosing the appropriate yield model. We illustrate our approach through several numerical examples and propose methods for estimating the newly defined block size.

Keywords

Block Size Negative Binomial Distribution Defect Distribution Average Cluster Size Area Cluster 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    I. Koren and C.H. Stapper, “Yield Models for Defect Tolerant VLSI Circuit: A Review,” Defect and Fault Tolerance in VLSI Systems, I. Koren (ed.), pp. 1-21, Plenum, 1989.Google Scholar
  2. [2]
    F.J. Meyer and D.K. Pradhan, “Modeling Defect Spatial Distribution,” IEEE Trans. on Computers, Vol. 38, pp. 538–546, April 1989.CrossRefGoogle Scholar
  3. [3]
    C.H. Stapper, “Correlation Analysis of Particle Clusters on Integrated Circuit Wafers,” IBM J. Res. Develop., Vol. 31, pp. 641–650, Nov. 1987.CrossRefGoogle Scholar
  4. [4]
    C.H. Stapper, “Small-Area Fault Clusters and Fault-Tolerance in VLSI Circuits,” IBM J. Res. Develop., Vol. 33, March 1989.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • Z. Koren
    • 1
  • I. Koren
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringUniversity of MassachusettsAmherstUSA

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