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An Efficient Reconfiguration Scheme for WSI of Cube-Connected Cycles with Bounded Channel Width

  • H. Y. Youn
  • A. D. Singh
  • J. H. Kim

Abstract

Wafer Scale Integration(WSI) technology1 allows us to realize the processor arrays of a certain interconnection topology on a single wafer. The performance improvement of the WSI processor arrays, compared to the uniprocessor system, is expected to be substantial. It was achieved by parallel processing using multiple processors and fast data communication between interacting processors. The off-chip communication delay is generally much bigger than that of on-chip communication. Therefore the performance improvement due to the WSI implementation of processor arrays will be significant for the problems requiring intensive communication between processors.

Keywords

Channel Width Processor Array Fault Distribution Rectangular Array Target Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • H. Y. Youn
    • 1
  • A. D. Singh
    • 1
    • 2
  • J. H. Kim
    • 1
    • 3
  1. 1.Dept. of Computer SciencesUniversity of North TexasDentonUSA
  2. 2.Dept. of Electrical & Computer EngineeringUniversity of MassachusettsAmherstUSA
  3. 3.The CACSUniversity of SW LouisianaLafayetteUSA

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