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Reliability Analysis of Application-Specific Architectures

  • K. Kubiak
  • W. K. Fuchs

Abstract

As the current trends in VLSI toward reduced feature size and accelerated clock rates continue, the reliability of VLSI circuits becomes an evermore important issue. For example, empirical studies have shown that as a technology undergoes constant-current scaling by a factor of α−1, the median time to failure due to metal electromigration will be diminished by a factor of α−2 [1]. In addition, an increase in clock rate requires that nodes be charged and discharged more rapidly, increasing the switching current in some technologies.

Keywords

Clock Cycle System Failure Clock Rate Delay Model VLSI Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    M.H. Woods, “MOS VLSI Reliability and Yield Trends,” Proceedings of the IEEE, pp. 1715-1729, Dec. 1986.Google Scholar
  2. [2]
    D.F. Frost and K.F. Poole, “RELIANT: A Reliability Analysis Tool for VLSI Interconnects,” IEEE J. Solid State Circuits, pp. 458-462, Apr. 1989.Google Scholar
  3. [3]
    B.J. Sheu, W.-J. Hsu, and B.W. Lee, “An Integrated Circuit Reliability Simulator—RELY,” IEEE J. Solid State Circuits, pp. 473-477, Apr. 1989.Google Scholar
  4. [4]
    C. Hu, P.K. Ho, P. Lee, J. Lee, N. Cheung, and B.K. Liew, “IC Reliability Prediction,” Proc. SRC TechCon, pp. 240-243, 1988.Google Scholar
  5. [5]
    T.S. Hohol and L.A. Glasser, “RELIC: A Reliability Simulator for Integrated Circuits,” Proc. Int’l Conference on Computer-Aided Design, pp. 517-520, 1986.Google Scholar
  6. [6]
    R. Burch, F. Najm, P. Yang, and D. Hocevar, “Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits,” Proc. 25th Design Automation Conference, pp. 294-299, 1988.Google Scholar
  7. [7]
    F. Najm, R. Burch, P. Yang, and I. Hajj, “CREST — A Current Estimator for CMOS Circuits,” Proc. Int’l Conference on Computer-Aided Design, pp. 204-207, 1988.Google Scholar
  8. [8]
    J.E. Hall, D.E. Hocevar, P. Yang, and M.J. McGraw, “SPIDER — A CAD System for Modeling VLSI Metallization Patterns,” IEEE Trans. CAD, pp. 1023-1030, Nov. 1987.Google Scholar
  9. [9]
    J.W. McPherson, “Stress Dependent Activation Energy,” Proc. Int’l Reliability Physics Symp., pp. 12-18, 1986.Google Scholar
  10. [10]
    D. LaCombe and E.L. Parks, “The Distribution of Elcctromigration Failures,” Proc. Int’l Reliability Physics Symp., pp. 1-6, 1986.Google Scholar
  11. [11]
    J. Lee, I.-C. Chen, and C. Hu, “Statistical Modeling of Silicon Dioxide Reliability,” Proc. Int’l Reliability Physics Symp., pp. 131-138, 1988.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • K. Kubiak
    • 1
  • W. K. Fuchs
    • 1
  1. 1.Computer Systems Group, Coordinated Science LaboratoryUniversity of Illinois at Urbana-ChampaignUrbanaUSA

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