Reliability Analysis of Application-Specific Architectures
As the current trends in VLSI toward reduced feature size and accelerated clock rates continue, the reliability of VLSI circuits becomes an evermore important issue. For example, empirical studies have shown that as a technology undergoes constant-current scaling by a factor of α−1, the median time to failure due to metal electromigration will be diminished by a factor of α−2 . In addition, an increase in clock rate requires that nodes be charged and discharged more rapidly, increasing the switching current in some technologies.
KeywordsClock Cycle System Failure Clock Rate Delay Model VLSI Circuit
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