APES: An Evaluation Environment of Fault-Tolerance Capabilities of Array Processors

  • F. Distante
  • V. Piuri


Design of VLSI and WSI array processors, a class of complex architectures, cannot avoid a detailed study of the fault/defect tolerance characteristics to prevent a consistent reduction of the production yield and a short functioning life of devices. These problems become particularly important when the application is critical and maintenance is difficult or impossible. In the APES environment some tools are available to evaluate statistically the the fault-tolerance capabilities of array processors and to simulate the behavior of such structures when faults occur.


Fault Injector Array Processor Fault Distribution Fault Occurrence Array Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    F. Distante, V. Piuri, “APES: an integrated system for behavioral design, simulation and evaluation of array processors”, IEEE Proc. ICCD88, 1988.Google Scholar
  2. 2.
    IEEE Design and Test of Computers, Special Issue on VHDL, April 1986.Google Scholar
  3. 3.
    R. Negrini, M.G. Sami, R. Stefanelli, Fault Tolerance through reconfiguration in VLSI and WSI arrays, The MIT Press, 1989.Google Scholar
  4. 4.
    J.A. Abraham, P. Banerjee, C.Y. Chen, W.K. Fuchs, S.Y. Kuo, A.L. Reddy, “Fault tolerance techniques for systolic arrays”, IEEE Comp. Magazine, July 1987.Google Scholar
  5. 5.
    F. Distante, R. Negrini, V. Piuri, “Simulated Annealing for defect tolerance in two-dimensional arrays”, Proc. IFIP Workshop on Wafer Scale Integration, 1987.Google Scholar
  6. 6.
    J.L. Patry, G. Saucier, “Design of an universal switching network for reconfigurable 2D-arrays”, Proc. 3rd Workshop on Wafer Scale Integration, June 1989.Google Scholar
  7. 7.
    P. Franzon, “Yield modeling for fault-tolerant arrays”, Systolic Arrays, Adam Hilger Ed., 1987.Google Scholar
  8. 8.
    J.A. Abraham, W.K. Fuchs, “Fault and error models for VLSI”, Proc. IEEE, May 1986.Google Scholar
  9. 9.
    R.M. Mangir, A. Avizienis, “Fault tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI design”, IEEE Trans. on Computers, July 1982.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • F. Distante
    • 1
  • V. Piuri
    • 1
  1. 1.Dept. of ElectronicsPolitecnico di MilanoMilanoItaly

Personalised recommendations