Extended Duplex Fault Tolerant System With Integrated Control Flow Checking

  • X. Delord
  • R. Leveugle
  • G. Saucier


Because majority voting provides both dependability and availability without any noticeable problem with validation, TMR (Triple Modular Redundancy) architectures are often used in highly dependable systems. However, these architectures have several drawbacks for onboard equipments: cost, weight, volume, power consumption and dissipation often lead to difficult problems. In other respects, if duplex architectures allow to reduce some of these problems, they do not provide the same availability characteristics.


Execution Unit Triple Modular Redundancy Instruction Code RISC Processor Concurrent Error Detection 
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  1. 1.
    A. Mahmood et al., Concurrent Fault Detection Using a Watchdog Processor and Assertions, International Test Conference, 1983, pp. 622-628.Google Scholar
  2. 2.
    A. Mahmood, E.J. McCluskey, Concurrent Error Detection Using Watchdog Processors — A Survey, IEEE Trans, on Computers, Vol. 37, No. 2, February 1988, pp. 160–174.CrossRefGoogle Scholar
  3. 3.
    M. Namjoo, E.J. McCluskey, Watchdog Processors and Capability Checking, FTCS-12,1982, pp. 245-248.Google Scholar
  4. 4.
    J.L. Lu, Watchdog Processors and Structural Integrity Checking, IEEE Trans. on Computers, Vol. C-31, No. 7, July 1982, pp. 681–685.CrossRefGoogle Scholar
  5. 5.
    M. Namjoo, Techniques for Concurrent Testing of VLSI Processor Operation, IEEE Test Conference, 1982, pp. 461-468.Google Scholar
  6. 6.
    T. Sridhar, S.M. Thatte, Concurrent Checking of Program Flow in VLSI Processors, IEEE Test Conference, 1982, pp. 191-199.Google Scholar
  7. 7.
    J.P. Shen, M.A. Schuette, On-Line Self-Monitoring Using Signatured Instruction Streams, International Test Conference, 1983, pp. 275-282.Google Scholar
  8. 8.
    K.D. Wilken, J.P. Shen, Embedded Signature Monitoring: Analysis and Technique, International Test Conference, 1987, pp. 324-333.Google Scholar
  9. 9.
    K. Wilken, J.P. Shen, Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors, International Test Conference, 1988, pp. 914-925.Google Scholar
  10. 10.
    M.A. Schuette, J.P. Shen, Processor Control Flow Monitoring Using Signatured Instruction Streams, IEEE Trans. on Computers, Vol. C-36, No. 3, March 1987, pp. 264–276.CrossRefGoogle Scholar
  11. 11.
    J. Sosnowski, Detection of Control Flow Errors Using Signature and Checking Instructions, International Test Conference, 1988, pp. 81-88.Google Scholar
  12. 12.
    N.R. Saxena, E.J. McCluskey, Control-Flow Checking Using Watchdog Assist and Extended-Precision Checksums, FTCS-19, 1989, pp. 428-435.Google Scholar
  13. 13.
    M.E. Schmid et al., Upset Exposure by means of Abstraction Verification, FTCS-192 1982, pp. 237-244.Google Scholar
  14. 14.
    U. Gunneflo et al., Evaluation of Error Detection Schemes using Fault Injection by Heavy-ion Radiation, FTCS-19, 1989, pp. 340–347.Google Scholar
  15. 15.
    D.A. Patterson, Reduced Instruction Set Computers, Communication of the ACM, January 1985, pp. 8-21.Google Scholar
  16. 16.
    W. Stallings, Reduced Instruction Set Computers, Computer Organization and Architecture, 1986, pp. 431-455.Google Scholar
  17. 17.
    Motorola Inc., MC88100 RISC Microprocessor User’s Manual, MC88100UM/AD Manual, 1988.Google Scholar
  18. 18.
    X. Delord, R. Leveugle, G. Saucier, Buit-in Concurrent Checking of ASICs, EuroASIC 89, Grenoble, France, January 1989, pp. 481-501.Google Scholar
  19. 19.
    J.B. Eifert, J.P. Shen, Processor Monitoring Using Asynchronous Signatured Instruction Streams, FTCS-14, 1984, pp. 394-399.Google Scholar
  20. 20.
    R. Leveugle, M. Soueidan, X. Delord, HSURF: A Microprocessor with Built-in Test Facilities for Highly Dependable Systems, 6th International Conference on Reliability and Maintainability, Strasbourg, France, October 1988, pp 188-193.Google Scholar
  21. 21.
    A. Schweitzer, Amélioration du niveau de sécurité des systèmes électroniques programmables par application du concept d’analyse de signature, Thèse de l’Université de Nancy, France, Mai 1987.Google Scholar
  22. 22.
    D.P. Siewiorek, R.S. Swarz, The Theory and Practice of Reliable System Design, Digital Press, 1982.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • X. Delord
    • 1
  • R. Leveugle
    • 1
  • G. Saucier
    • 1
  1. 1.Institut National Polytechnique de Grenoble/CSIGrenoble CedexFrance

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