Instruction Fetch Hardware

  • Paul Chow
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 81)


One of the difficult tasks of keeping a high speed processor busy is to make sure that it has a constant supply of instructions and to make sure that they are supplied quickly. This requires a very high bandwidth for both instructions and data. For MIPS-X, when both an instruction and data are required, the peak bandwidth required is 160 Mbytes/s. Building a memory system to support this would not be simple and transferring this amount of data across the pins of a VLSI chip would have been difficult with the packaging technology available at the time. MIPS-X uses an on-chip instruction cache to reduce the memory bandwidth requirements. Putting an instruction cache on-chip also makes it possible to fetch new instructions every cycle if the instructions are in the cache.


Program Counter Instruction Cache Ring Counter Sense Amplifier Pass Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1989

Authors and Affiliations

  • Paul Chow
    • 1
  1. 1.University of TorontoCanada

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