Abstract
MIPS-X is the successor to the MIPS project at Stanford University. Like its predecessor, it is a single chip VLSI processor that uses a simplified instruction set, pipelining and a software code reorganizer to obtain high performance. Key features include single-cycle execution of all instructions, use of an on-chip 512-word instruction cache, coprocessor support, and support for multiprocessor operation. The processor is designed in a 2 µm, 2-level metal CMOS technology, and will have a cycle time of 50 ns.
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© 1989 Springer Science+Business Media New York
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Chow, P. (1989). Introduction. In: Chow, P. (eds) The MIPS-X RISC Microprocessor. The Springer International Series in Engineering and Computer Science, vol 81. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6762-9_1
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DOI: https://doi.org/10.1007/978-1-4757-6762-9_1
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