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SystemVerilog Design Hierarchy

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

This chapter presents the many enhancements to Verflog that SystemVerilog adds for representing and working with design hierarchy. The topics that are discussed include:
  • Module prototypes

  • Nested modules

  • Simplified netlists of module instances

  • Netlist aliasing

  • Passing values through module ports

  • Port connections by reference

  • Enhanced port declarations

  • Parameterized data types and polymorphism

  • Variable declarations in blocks

Keywords

Data Type Vector Size Module Definition Module Instance Input Wire 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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