Modeling Finite State Machines with SystemVerilog
SystemVerilog enables modeling at a higher level of abstraction through the use of 2-state data types, enumerated types, and user-defined types. These are complemented by new specialized always procedural blocks, always_comb, always_ff and always_latch. These and other new modeling constructs have been discussed in the previous chapters of this book.
KeywordsState Machine Finite State Machine Case Expression Procedural Block Semantic Check
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