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Modeling Finite State Machines with SystemVerilog

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

SystemVerilog enables modeling at a higher level of abstraction through the use of 2-state data types, enumerated types, and user-defined types. These are complemented by new specialized always procedural blocks, always_comb, always_ff and always_latch. These and other new modeling constructs have been discussed in the previous chapters of this book.

Keywords

State Machine Finite State Machine Case Expression Procedural Block Semantic Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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