SystemVerilog adds several new operators and procedural statements to the Verilog language that allow modeling at a more abstract, C-like level. Additional enhancements convey the designer’s intent, helping to ensure that all software tools interpret the procedural statements in the same way. This chapter covers these operators and procedural statements, and offers guidelines on how to properly use these new constructs.
KeywordsDecrement Operator Decision Sequence Combinational Logic Race Condition Sequential Logic
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