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SystemVerilog Arrays, Structures and Unions

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

SystemVerilog adds several enhancements to Verilog for representing large amounts of data. The Verilog array constructs are extended both in how data can be represented and for operations on arrays. Structure and union data types have been added to Verilog as a means to represent collections of variables.

Keywords

Data Type Packed Structure Array Wire Packed Array Sparse Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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