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A Complete Design Modeled with SystemVerilog

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

Abstract

This chapter brings together the many concepts presented in previous chapters of this book, and shows how the SystemVerilog enhancements to Verilog can be used to model large designs much more efficiently than with the standard Verilog HDL. The example presented in this chapter shows how SystemVerilog can be used to model at a much higher level of data abstraction than Verilog, and yet be fully synthesizable.

Keywords

Asynchronous Transfer Mode Forwarding Node Packet Type Packed Union Test View 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2004

Authors and Affiliations

  • Stuart Sutherland
  • Simon Davidmann
  • Peter Flake

There are no affiliations available

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