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Verilog-2001 Behavioral and Synthesis Enhancements

  • Clifford E. Cummings
Chapter

Abstract

The Verilog-2001 Standard includes a number of enhancements that are targeted at simplifying designs, improving designs and reducing design errors.

This paper details important enhancements that were added to the Verilog-2001 Standard that are intended to simplify behavioral modeling and to improve synthesis accuracy and efficiency. Information is provided to explain the reasons behind the Verilog-2001 Standard enhancement implementations

Keywords

Constant Function Synthesis Tool Multidimensional Array Compiler Directive Continuous Assignment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std PI3641D5Google Scholar
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    Douglas L. Perry, VHDL, McGraw-Hill, Inc., 1994, p. 1.Google Scholar
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    IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Computer Society, IEEE Std 1364–1995Google Scholar
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    www.chris.spear.netGoogle Scholar
  5. [5]
    Don Mills and Clifford E. Cummings, “RTL Coding Styles That Yield Simulation and Synthesis Mismatches,” SNUG 99 (Synopsys Users Group San Jose, CA, 1999) Proceedings, section-TA2 (Is paper), March 1999.Google Scholar
  6. [6]
    Clifford E. Cummings, “full_case parallel_case”, the Evil Twins of Verilog Synthesis,’ SNUG 99 Boston (Synopsys Users Group Boston, MA, 1999) Proceedings, section-FA1 (2nd paper), October 1999.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Clifford E. Cummings
    • 1
  1. 1.Sunburst Design, IncBeavertonUSA

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