Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook
This paper describes the author’s experience using the VHDL language and the productivity enhancement tool DesignBook in an FPGA design consisting of a state machine-based DSP I/O controller for the air data computers in a modem Air Force fighter jet. The computers are based on a digital signal processor, which has little in the way of general purpose I/O. The design implemented a memory-mapped I/O controller for the control of DSP peripherals including external program memory, non-volatile storage, temperature and pressure sensing modules, communication transceivers, and DSP boot memory.
The design was implemented in an Actel A42MX series FPGA. The design implemented many state loops for the control of all the DSP peripherals. The state diagrams were input using the state diagram editor in DesignBook and tied together in a hierarchical fashion using the block diagram editor. Other hierarchical blocks were generated, interconnected, and simulated until the complete FPGA design was entered and verified.
KeywordsClock Cycle Digital Signal Processor State Diagram Timing Diagram State Loop
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