Hardware Supported Sorting: Design and Tradeoff Analysis
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We investigate cost/performance tradeoffs for hybrid sorting algorithms that use a mixture of sequential merge sort and systolic insertion sort techniques. We propose a scalable architecture for integer sorting that consists of a uniprocessor and an FPGA-based parallel systolic co-processor. Speedups obtained analytically and experimentally and depending on hardware (cost) constraints are determined as a function of time constants of the uniprocessor and the co-processor.
KeywordsHybrid Algorithm System Design Automation Speedup Curve FPGA Chip Sorting Device
Unable to display preview. Download preview PDF.
- K. E. Batcher. Sorting networks and their applications. In AFIPS Conf. Proc. 32, pages 307–314, 1968.Google Scholar
- D. E. Knuth. The Art of Computer Programming, Volume 3: Sorting and Searching. Addison-Wesley, Reading, Massachusetts, 2nd edition, 1998.Google Scholar
- C. E. Leiserson. Systolic priority queues. In Proc. Conf. Very Large Scale Integration: Architecture, Design, Fabrication, pages 199–214, 1979.Google Scholar
-  J. Teich. A Compiler for Application-Specific Processor Arrays. Shaker (Reihe Elektrotechnik).Zugl. Saarbrücken, Univ. Diss, ISBN 3–86111–701–0, Aachen, Germany, 1993.Google Scholar
- L. Thiele. On the design of piecewise regular processor arrays. In Proc. IEEE Symp. on Circuits and Systemspages 2239–2242, 1989.Google Scholar
- L. Thiele. CAD for signal processing architectures. In The State of the Art in Computer Systems and Software Engineering (P. Dewilde, ed.), Boston: Kluwer Academic Publishers, 1992.Google Scholar