Synthesis and Optimization of Digital Hardware/Software Systems

  • Jürgen Teich


In this introductory paper to the field, it is our goal to provide a new unified look at synthesis problems that is independent from the level of abstraction like system, RTL, and logic (for refinements targeted to hardware), or process- and basic block level (for refinements targeted to software). For each level of our model called ”double roof”, synthesis requires the solution of three basic problems, namely allocation (of resources), binding, and scheduling Based on the ”double roof” model, we present a graph-based formulation of the tasks of system-synthesis: Contrary to former approaches that consider system-synthesis as a bi-partition problem (e.g., earlier hardware/software partitioning algorithms), we consider also as well the allocation of components like micro- and hardware coprocessors as part of the optimization problem as scheduling of tasks including communication scheduling. The approach is flexible enough to be applied to different other abstraction levels. Finally, we introduce the problem of design space exploration as a new challenge in synthesis. For the typically multi-objective nature of synthesis problems, not only one optimum is wanted, but an exploration of a complete front of optimal solutions called Pareto points.


Design Point Dependence Graph Abstraction Level System Design Automation Design Space Exploration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    T. Bäck, D. B. Fogel, and Z. Michaelevicz. Handbook on Evolutionary Computation. Inst. of Phy. Publ., Bristol, 1997.Google Scholar
  2. [2]
    F. Balarin, A. Jurecska, and H. H. et al. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Press, Boston, 1997.CrossRefGoogle Scholar
  3. [3]
    A. Benveniste and G. Berry. The synchronous approach to reactive and real-time systems. Proceedings of the IEEE, 79 (9): 1270–1282, 1991.CrossRefGoogle Scholar
  4. [4]
    T. Blickle, J. Teich, and L. Thiele. System-level synthesis using Evolutionary Algorithms. J. Design Automation for Embedded Systems, 3 (1): 23–58, January 1998.CrossRefGoogle Scholar
  5. [5]
    J. Buck, S. Ha, E. Lee, and D. Messerschmitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. International Journal on Computer Simulation, 4:155–182,1991. Google Scholar
  6. [6]
    F. Cieslok, H. Esau, and J. Teich. EXPLORA- a tool for generic design space explo-ration. Technical report, TR No. 2/00, Computer Engineering Laboratory, University of Paderborn, Feb. 2000.Google Scholar
  7. [7]
    L. Davis. Handbook of Genetic Algorithms, chapter 6, pages 72–90. Van Nostrand Reinhold, New York, 1991.Google Scholar
  8. [8]
    D. Gajski, N. Dutt, A. Wu, and S. Lin. High Level Synthesis: Introduction to Chip and System Design. Kluwer, Norwell, Massachusetts, 1992.Google Scholar
  9. [9]
    N. Halbwachs. Synchronous Programming of Reactive Systems. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1993.Google Scholar
  10. [10]
    D. Harel. Statecharts: A visual formalism for complex systems. Science of Computer Programming, 8, 1987.Google Scholar
  11. [11]
    C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall, Englewood Cliffs, NJ, 1985.zbMATHGoogle Scholar
  12. [12]
    S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(45981: 671–680, 1983.Google Scholar
  13. [13]
    R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7 (2): 32–43, Apr. 1990.CrossRefGoogle Scholar
  14. [14]
    E. Lee and D. Messerschmitt. Synchronous dataflow. Proceedings of the IEEE, 75 (9): 1235–1245, 1987.CrossRefGoogle Scholar
  15. [15]
    E. A. Lee and T. M. Parks. Dataflow Process Networks. Technical Report UCB/ERL 94/53, Dept. of EECS, UC Berkeley, Berkeley, CA 94720, U.S.A., 1994.Google Scholar
  16. [16]
    E. A. Lee and T. M. Parks. Dataflow process networks. Proceedings of the IEEE, 83 (5): 773–799, 1995.CrossRefGoogle Scholar
  17. [17]
    S. Ritz, M. Pankert, and H. Meyr. High level software synthesis for signal processing systems. In Proc. Int. Conf. on Application-Specific Array Processors, pages 679–693, Berkeley, CA, 1992.CrossRefGoogle Scholar
  18. [18]
    R. Saracco, J. R. W. Smith, and R. Reed. Telecommunications systems engineering using SDL. North-Holland, Elsevier, Amsterdam, 1989.Google Scholar
  19. [19]
    K. Strehl, L. Thiele, D. Ziegenbein, R. Ernst, and J. Teich. Scheduling hardware/software systems using symbolic techniques. In Proceedings of the 7th International Workshop on Hardware/Software Codesign (CODES’99), pages 173–177, Rome, Italy, May 3–5, 1999.Google Scholar
  20. [20]
    J. Teich. Digitale Hardware/Software-Systeme: Synthese und Optimierung. Springer-Lehrbuch, Heidelberg, New York, Tokio, 1997.Google Scholar
  21. [21]
    J. Teich, E. Zitzler, and S. S. Bhattacharyya. 3D exploration of software schedules for DSP algorithms. In Proc. CODES’99, the 7th Int. Workshop on Hardware/Software Co-Design, Rome, Italy, May 1999.Google Scholar
  22. [22]
    J. Teich, E. Zitzler, and S. S. Bhattacharyya. 3d exploration of uniprocessor schedules for DSP algorithms. Technical Report 56, Institute TIK, ETH Zurich, Switzerland, January 1999.Google Scholar
  23. [23]
    P. P. Vaidyanathan. Multirate Systems and Filter Banks. Prentice Hall, 1993.Google Scholar
  24. [24]
    E. Zitzler, J. Teich,, and S. S. Bhattacharyya. Evolutionary algorithm based exploration of software schedules for digital signal processors. In Proc. GECCO’99, the Genetic and Evolutionary Computation Conference, Orlando, U.S.A., July 1999.Google Scholar
  25. [25]
    E. Zitzler, J. Teich, and S. Bhattacharyya. Multidimensional exploration of software implementations for DSP algorithms. J. on VLSI Signal Processing, 24: 83–98, 2000.zbMATHCrossRefGoogle Scholar
  26. [26]
    E. Zitzler, J. Teich, and S. Bhattacharyya. Evolutionary algorithms for the synthesis of embedded software. IEEE Trans. on VLSI Systems, to appear, 2000.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Jürgen Teich
    • 1
  1. 1.DatentechnikUniversität PaderbornPaderbornGermany

Personalised recommendations