A 3-V Wideband CMOS Switched-Current A/D-Converter

  • Bengt E. Jonsson
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 561)


The simulated and measured performance of an experimental wideband CMOS A/D converter design is presented in this chapter. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f in = 1.83 MHz, the measured SFDR = 60.3 dB and SNDR = 46.5 dB at f s = 3 MHz. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 μm CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR ≥ 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.


Input Frequency Spectral Performance Digital Correction Input Bandwidth Digital CMOS Process 


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Copyright information

© Springer Science+Business Media Dordrecht 2000

Authors and Affiliations

  • Bengt E. Jonsson
    • 1
  1. 1.Ericsson Radio Systems ABStockholmSweden

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