During the last decade, the telecommunication market and especially the mobile telecommunication systems have known an unprecedented growth. New services are constantly being introduced since the evolution towards smaller technologies makes it possible to integrate millions of transistors on a single chip. The digital designers create new DSP (Digital Signal Processing) architectures that allow complex algorithms to be implemented at very high computational speeds. In parallel, analog designers have been putting an enormous effort in developing high speed, low distortion blocks that in combination with the digital building blocks will result in the high performance telecommunication systems of tomorrow. However, this implies that the design of the interface circuit between the analog and digital part of the system -the D/A converter and the A/D converter-is becoming more challenging in time. Besides a highly accurate circuit also a high operation speed achieved at a low power consumption are demanded. The combination of these constraints poses a real challenge for the designers of these circuits. Furthermore, additional problems -like the substrate noise coupling from the digital to the analog part on the chip and the scaling of the power supply voltage- add to the complexity of the design.
KeywordsInterface Circuit Current Steering High Operation Speed Telecommunication Market Spurious Free Dynamic Range
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