An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch
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The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches. An algorithm has been proposed for testing the cores using the TAM switch architecture. In addition, a scheme for testing the interconnections between cores in parallel is also presented. Experiments have been carried out on several synthetic SOC benchmarks. Results show significant optimization of area overhead as well as test time.
Keywordssystem-on-chip TAM switch interconnect testing
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