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An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch

  • Subhayu Basu
  • Indranil Sengupta
  • Dipanwita Roy Chowdhury
  • Sudipta Bhawmik
  • Krishnendu Chakrabarty
Chapter
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches. An algorithm has been proposed for testing the cores using the TAM switch architecture. In addition, a scheme for testing the interconnections between cores in parallel is also presented. Experiments have been carried out on several synthetic SOC benchmarks. Results show significant optimization of area overhead as well as test time.

Keywords

system-on-chip TAM switch interconnect testing 

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Subhayu Basu
    • 1
  • Indranil Sengupta
    • 2
  • Dipanwita Roy Chowdhury
    • 2
  • Sudipta Bhawmik
    • 3
  • Krishnendu Chakrabarty
  1. 1.Princeton UniversityUSA
  2. 2.Department of Computer Science and EngineeringIndian Institute of TechnologyKharagpurIndia
  3. 3.Agere SystemsHolmdelUSA

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