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CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

  • Mounir Benabdenbi
  • Walid Maroufi
  • Meryem Marzouki
  • Krishnendu Chakrabarty
Chapter
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features. This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation. These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.

Keywords

SoC test control test access mechanism TAPed cores P1500 wrappers I/O bandwidth 

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References

  1. 1.
    M. Benabdenbi, W. Maroufi, and M. Marzouki, “Cas-Bus: A Scalable and Reconfigurable Test Acces Mechanism for Systems on a Chip,” in IEEE Design Automation and Test in Europe (DATE), Paris, France, March 2000, pp. 141–145.CrossRefGoogle Scholar
  2. 2.
    M. Benabdenbi, W. Maroufi, and M. Marzouki, “Testing Taped Cores and Wrapped Cores with the Same Test Access Mechanism,” in IEEE Design Automation and Test in Europe (DATE), Munich, Germany, March 2001, pp. 150–155.Google Scholar
  3. 3.
    D. Bhattacharya, “Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit,” in IEEE VLSI Test Symposium (VTS)Dana Point (CA), USA, April 1998, pp. 814. Google Scholar
  4. 4.
    K. Chakrabarty, “Design of System on a Chip Test Access Architectures Under Place-and-Route and Power Constraints,” in IEEE/ACM Design Automation Conference (DAC)Los Angeles (CA), USA, June 2000, pp. 432–437. Google Scholar
  5. 5.
    K. Chakrabarty, “Optimal Test Access Architectures for System on a Chip,” ACM Trans. Design Automation of Electronic Systemsvol. 6, no. 1, pp. 26–49, Jan. 2001. Google Scholar
  6. 6.
    B. Dervisoglu and J. Swamy, “A Novel Approach for Designing a Hierarchical Test Access Controller for Embedded Core Designs in an SoC Environment,” in 4th IEEE International Workshop on Testing Embedded Core-Based System-Chips (TECS), Montreal (QC), Canada, May 2000, pp. 1.4.1–1. 4. 7.Google Scholar
  7. 7.
    C. Feige and C. Wouters, “Integration of Structural Test Methods into an Architecture Specific Core-Test Approach.’ in 2nd IEEE International Workshop on Testing Embedded Core-Based System-Chips (TECS)Washington (DC), USA, Oct. 1998, pp. 5.2.1–5.2.8. Google Scholar
  8. 8.
    S.K. Goel and E.J. Marinissen, “TAM Architectures and their Implication on Test Application Time,” in IEEE International Workshop on Testing Embedded Core-Based Systems (TECS)Marina del Rey (CA), USA, May 2001, pp. 3.3.1–3.3.10. Google Scholar
  9. 9.
    IEEE P1500 Standard for Embedded Core Test Web Site, http://grouper.ieee.org/groups/1500.Public Informations.
  10. 10.
    V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Test Wrapper and Test Acces Mechanism Co-Optimization for System on a Chip,” in IEEE International Test Conference (ITC), Baltimore, MD, USA, Oct. 2001, pp. 1023–1032.Google Scholar
  11. 11.
    A. Jas, J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/Decompression Using Statistical Coding,” in 17th IEEE VLSI Test Symposium (VTS)San Diego (CA), USA, April 1999. Google Scholar
  12. 12.
    A. Jas and N.A. Touba, “Test Vector Decompression Via Cyclical Scan Chains and its Application to Testing Core-Based Designs,” in IEEE International Test Conference (ITC), Washington (DC), USA, 1998, pp. 458–464.Google Scholar
  13. 13.
    E. Larsson and Z. Peng, “An Integrated System on a Chip Test Framework,” in IEEE Design Automation and Test in Europe Conference (DATE)Munich, Germany, March 2001, pp. 138144. Google Scholar
  14. 14.
    D.A. Lelewer and D.S. Hirschberg, “Data Compression,” ACM Computing Surveys (CSUR), vol. 19, no. 3, pp. 261–296, Sept. 1987.zbMATHCrossRefGoogle Scholar
  15. 15.
    LIP6-ASIM, Alliance CAD System. http://www-asim.lip6. fr/alliance/. University Paris 6-France.
  16. 16.
    E.J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” in IEEE International Test Conference (ITC), Washington (DC), USA, Oct. 1998.Google Scholar
  17. 17.
    E.J. Marinissen and M. Lousberg, “The Role of Test Protocol in Testing Embedded Core-Based System ICs,” in IEEE European Test Workshop (ETW)Constance, Germany, May 1999, pp. 7075. Google Scholar
  18. 18.
    E.J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, “Towards a Standard for Embedded Core Test: An Example,” in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept. 1999.Google Scholar
  19. 19.
    W. Maroufi, M. Benabdenbi, and M. Marzouki, “Solving the UO Bandwith Problem in System on a Chip Testing,” in XIII Symposium on Integrated Circuits and System Design (SBCCI)Manaus (AM), Brazil, Sept. 2000, pp. 9–14. Google Scholar
  20. 20.
    W. Maroufi, M. Benabdenbi, and M. Marzouki, “Controlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for Systems on a Chip Testing,” in 4th IEEE International Workshop on Testing Embedded Core-Based System-Chips (TECS),Montreal (QC), Canada, May 2000, pp. 4.5.1–4.5.6.Google Scholar
  21. 21.
    Synopsys, Synopsys Design Compiler Family. http://www. synopsys.com/products/logic/logic.html.Synopsys,Inc.
  22. 22.
    J. van Beers and H. van Herten, “Test Features of a Core-Based Co-Processor Array for Video Applications,” in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept 1999, pp. 638–647.Google Scholar
  23. 23.
    E Varma and S. Bhatia, “A Structured Test Reuse Methodology for Core-Based System Chips,” in IEEE International Test Conference (ITC), Washington (DC), USA, Oct. 1998.Google Scholar
  24. 24.
    F. Wajsbiirt, J.L. Desbarbieux, C. Spasevski, S. Penain, and A. Greiner, “An Integrated PCI Component for IEEE 1355,” in European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition, Florence, Italy, Nov. 1997.Google Scholar
  25. 25.
    L. Whetsel, “An IEEE 1149.1 Based Test Acces Architecture for ics with Embedded Cores,” in IEEE International Test Conference (ITC), Washington (DC), USA, Nov. 1997, pp. 69–78.Google Scholar
  26. 26.
    L. Whetsel, `Addressable Test Ports an Approach to Testing Embedded Cores,“ in IEEE International Test Conference (ITC), Atlantic City (NJ), USA, Sept. 1999, pp. 1055–1064.Google Scholar
  27. 27.
    L. Whetsel and M. Ricchetti, “Tapping into IEEE P1500 Domains,” in 5th IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Los Angeles (CA), USA, May 2001.Google Scholar
  28. 28.
    LH. Witten, R.M. Neal, and J.G. Cleary, “Arithmetic Coding for Data Compression,” Communications of the ACM, vol. 30, no. 6, pp. 520–540, June 1987.CrossRefGoogle Scholar
  29. 29.
    Y. Zorian, “Testing the Monster Chip,” in IEEE Spectrum, July 1999, pp. 54–60.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Mounir Benabdenbi
    • 1
  • Walid Maroufi
    • 1
  • Meryem Marzouki
    • 1
  • Krishnendu Chakrabarty
  1. 1.LIP6 Laboratory, Couloir 55-65Paris Cedex 05France

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