Skip to main content
SpringerLink
Log in
Book cover

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation pp 71–90Cite as

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

  • Chapter

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 21))

Abstract

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to sy stem-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. Aerts, “Test Time Reduction Algorithms for Core-Based IC,,” Master’s thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, April 1998.

    Google Scholar 

  2. R. Arendsen and M. Lousberg, “Core Based Test for a System on Chip Architecture Framework,” In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Washington, DC, Oct. 1998, Paper 5.1.

    Google Scholar 

  3. F. Beenker, B. Bennetts, and L. Thijssen, Testability Concepts for Digital ICs—The Macro Test Approach, vol. 3 of Frontiers in Electronics Testing, Boston, USA: Kluwer Academic Publishers, 1995.

    Google Scholar 

  4. F. Beenker, K. van Eerdewijk, R. Gerritsen, F. Peacock, and Max van der Star, “Macro Testing: Unifying IC and Board Test,” IEEE Design & Test of Computers, vol. 3, no. 4, pp. 26–32, Dec. 1986.

    Article  Google Scholar 

  5. M. Boosten and H. Jacobs, “Test Protocol Expansion: Memory Handling and Efficiency Improvements,” Master’s thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, June 1994.

    Google Scholar 

  6. F. Bouwman, S. Oostdijk, R. Stans, B. Bennetts, and F. Beenker, “Macro Testability; The Results of Production Device Applications,” in Proceedings IEEE International Test Conference (1rC), Sept. 1992, pp. 232–241.

    Google Scholar 

  7. K Chakrabarty, “Test Scheduling for Core-Based Systems,” in Proceedings International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 1999, pp. 391–394

    Google Scholar 

  8. K. Chakrabarty, “Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming,” IEEE Transactions on Computer-Aided Design, vol. 19, no. 10, pp. 1163–1174, Oct. 2000.

    Article  Google Scholar 

  9. M.R. Garey and D.S. Johnson, Computers and Intractability —A Guide to the Theory of NP-Completeness, San Francisco: W.H. Freeman and Company, 1979.

    MATH  Google Scholar 

  10. I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Testing Technique for Core-Based System-on-Chip,” in Proceedings ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1998. Association for Computing Machinery, Inc., pp. 542–547.

    Google Scholar 

  11. I. Ghosh, N.K. Jha, and S. Dey, “A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Nov. 1997, pp. 50–59.

    Google Scholar 

  12. S. K. God and E.J. Marinissen, “Cluster-Based Test Architecture Design for System-on-Chip,” in Proceedings IEEE VLSI Test Symposium (VTS), Monterey, CA, April 2002, pp. 259–264.

    Google Scholar 

  13. Mentor Graphics, “Solving the Challenges of Testing Small Embedded Cores and Memories Using FastScan MacroTest,” White Paper, Jan. 2000.

    Google Scholar 

  14. R.K. Gupta and Y. Zorian, “Introducing Core-Based System Design,” IEEE Design and Test of Computers, vol. 14, no. 4, pp. 1525, Dec. 1997.

    Google Scholar 

  15. N.G. Hall and C. Sriskandarajah, “A Survey of Machine Scheduling Problems with Blocking and no-Wait in Process,” Operations Research, vol. 44, pp. 510–525, 1996.

    Article  MathSciNet  MATH  Google Scholar 

  16. IEEE Computer Society, IEEE Standard Test Access Port and Boundary-Scan Architecture—IEEE Std. 1149.1–1990, New York: IEEE, June 1993.

    Google Scholar 

  17. V. Iyengar and K. Chakrabarty, “Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip,” in Proceedings IEEE VLSI Test Symposium (VTS), Marina del Rey, CA, May 2001, pp. 368–374.

    Google Scholar 

  18. V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores,” Journal of Electronic Testing: Theory and Applications, vol. 18, no. 2, pp. 213–230, April 2002.

    Article  Google Scholar 

  19. R. Kapur et al., “CTL—The Language for Describing Core-Based Test,” in Proceedings IEEE International Test Conference (ITC), Baltimore, MD, Oct. 2001, pp. 131–139.

    Google Scholar 

  20. M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Norwell, Massachusetts: Kluwer Academic Publishers, June 1999.

    Google Scholar 

  21. E. Larsson and Z. Peng, “An Integrated System-on-Chip Test Framework,” in Proceedings Design, Automation, and Test in Europe (DATE), Munich, Germany, March 2001, pp. 138–144.

    Google Scholar 

  22. E. Larsson and Z. Peng, “System-on-Chip Test Parallelization under Power Constraints,” in Digest of Papers of IEEE European Test Workshop (ETW), Saltsjobaden, Sweden, May 2001, pp. 281–283.

    Google Scholar 

  23. E.J. Marinissen, “Philips’ Approach to Core-Based System Chip Testing,” in Proceedings IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Montpellier, France, Dec. 2001, LIRMM, France, pp. 201–210.

    Google Scholar 

  24. E.J. Marinissen and J. Aerts, “Test Protocol Scheduling for Embedded-Core Based System ICs,” in Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Washington, DC, Oct. 1998, Paper 5. 3.

    Google Scholar 

  25. E.J. Marinissen et al., “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 284–293.

    Google Scholar 

  26. E.J. Marinissen et al. “On IEEE P1500’s Standard for Embedded Core Test,” Journal of Electronic Testing: Theory and Applications, vol. 18, no. 4, Aug. 2002, pp. 365–383.

    Google Scholar 

  27. E.J. Marinissen, R. Kapur, and Y. Zorian, “On Using IEEE P1500 SECT for Test Plug-n-Play,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Oct. 2000, pp. 770777.

    Google Scholar 

  28. E.J. Marinissen, K. Kuiper, and C. Wouters, “Test Protocol Expansion in Hierarchical Macro Testing,” in Proceedings IEEE European Test Conference (ETC), Rotterdam, The Netherlands, April 1993, pp. 28–36.

    Chapter  Google Scholar 

  29. E.J. Marinissen and M. Lousberg, “Macro Test: A Liberal Test Approach for Embedded Reusable Cores,” in Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Washington, DC, Nov. 1997, Paper 1. 2.

    Google Scholar 

  30. E.J. Marinissen and M. Lousberg, “The Role of Test Protocols in Testing Embedded-Core-Based System ICs,” in Proceedings IEEE European Test Workshop (ETW), Konstanz, Germany, May 1999, pp. 70–75.

    Google Scholar 

  31. E.J. Marinissen and H. Vranken, “On the Role of DîT in IC-ATE Matching,” in Digest of IEEE International Workshop on Test Resource Partitioning, Paper 1. 2, Baltimore, MD, Nov. 2001.

    Google Scholar 

  32. E.J. Marinissen and Y. Zorian, “Challenges in Testing Core-Based System ICs,” IEEE Communications Magazine, vol. 37, no. 6, pp. 104–109, June 1999.

    Article  Google Scholar 

  33. J. Monzel and E. Orosz, “Testing ‘Systems-on-a-Chip’ in a Low Cost ASIC Test Environment,” in Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), Washington, DC, November 1997, Paper 5. 1.

    Google Scholar 

  34. M. Pinedo, Scheduling—Theory, Algorithms, and Systems, Englewood Cliffs, New Jersey: Prentice Hall, 1995.

    Google Scholar 

  35. P. Rosinger, B. Al-Hashimi, and N. Nicolici, “Power Constrained Test Scheduling Using Power Profile Manipulation,” in Proceedings International Symposium on Circuits and Systems (ISCAS), vol. V, May 2001, pp. V251–V254.

    Google Scholar 

  36. D.E. Ross, T. Wood, and G. Giles, “Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Oct. 2000, pp. 691–700.

    Google Scholar 

  37. M. Sugihara, H. Date, and H. Yasuura, “A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 465472.

    Google Scholar 

  38. J. van Beers and H. van Herten, “Test Features of a Core-Based Co-Processor Array for Video Applications,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Sept. 1999, pp. 638–647.

    Google Scholar 

  39. M. van Wijngaarden, “Test Protocol Expansion: Models and Solution Approaches,” Master’s thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, Aug. 1993.

    Google Scholar 

  40. B. Vermeulen, S. Oostdijk, and E Bouwman, “Test and Debug Strategy of the PNX8525 NexperiaTM Digital Video Platform System Chip,” in Proceedings IEEE International Test Conference (ITC), Baltimore, MD, Oct. 2001, pp. 121–130.

    Google Scholar 

  41. Y. Zorian and E.J. Marinissen, “System Chip Test: How Will It Impact Your Design?” in Proceedings ACM/IEEE Design Automation Conference (DAC), Los Angeles, June 2000. Association for Computing Machinery, Inc., pp. 136141.

    Google Scholar 

  42. Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 130–143.

    Google Scholar 

  43. Y. Zorian, E.J. Marinissen, and S. Dey, “Testing EmbeddedCore-Based System Chips,” IEEE Computer, vol. 32, no. 6, pp. 52–60, June 1999.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Philips Research Laboratories, IC Design—Digital Design & Test, Prof. Holstlaan 4, M/S WAY-41, 5656 AA, Eindhoven, The Netherlands

    Erik Jan Marinissen

Authors
  1. Erik Jan Marinissen
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Duke University, USA

    Krishnendu Chakrabarty

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer Science+Business Media New York

About this chapter

Cite this chapter

Marinissen, E.J. (2002). The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. In: Chakrabarty, K. (eds) SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Frontiers in Electronic Testing, vol 21. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6527-4_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-6527-4_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5307-0

  • Online ISBN: 978-1-4757-6527-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation