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On-Chip Clock Faults’ Detector

  • Cecilia Metra
  • Michele Favalli
  • Stefano Di Francescantonio
  • Bruno Riccò
  • Krishnendu Chakrabarty
Chapter
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

This paper proposes an on-chip detector for the on-line testing of faults affecting clock signals and making them change with incorrect duty-cycle. Our scheme is particularly suitable to be integrated within SystemsOn-a-Chip (SOCs), in order to avoid their possible incorrect operation because of faults affecting clock signals, thus solving their extreme criticality in clock faults’ testing. In particular, our detector is suitable to be applied to clock signals within each SOC digital core, to the clock signals at the interface between the diverse cores, as well as to those driving the DFT and BIST structures used to perform the SOC test. Our scheme features self-checking ability with respect to its possible internal faults belonging to a realistic set including stuck-ats, transistor stuck-ons, stuck-opens and resistive bridgings.

Keywords

clock faults systems-on-a-chip on-line testing 

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Cecilia Metra
    • 1
  • Michele Favalli
    • 2
  • Stefano Di Francescantonio
    • 1
  • Bruno Riccò
    • 1
  • Krishnendu Chakrabarty
  1. 1.DEIS—University of BolognaBolognaItaly
  2. 2.DI—University of FerraraFerraraItaly

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