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Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

  • Mehrdad Nourani
  • Amir Attarha
  • Krishnendu Chakrabarty
Chapter
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.

Keywords

built-in self-test high-speed interconnect integrity fault integrity loss interconnect testing model order reduction noise detection signal integrity skew detection system-on-chip test pattern generation transfer function matrix 

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Mehrdad Nourani
    • 1
  • Amir Attarha
    • 1
  • Krishnendu Chakrabarty
  1. 1.Center for Integrated Circuits & SystemsThe University of Texas at DallasRichardsonUSA

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