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Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

  • Chen Li
  • Xiaoliang Bai
  • Sujit Dey
  • Krishnendu Chakrabarty
Chapter
  • 197 Downloads
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.

Keywords

interconnect crosstalk self-test processor 

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Chen Li
    • 1
  • Xiaoliang Bai
    • 1
  • Sujit Dey
    • 1
  • Krishnendu Chakrabarty
  1. 1.Department ECEUniversity of California at San DiegoLa JollaUSA

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