Advertisement

On IEEE P1500’s Standard for Embedded Core Test

  • Erik Jan Marinissen
  • Rohit Kapur
  • Maurice Lousberg
  • Teresa McLaurin
  • Mike Ricchetti
  • Yervant Zorian
  • Krishnendu Chakrabarty
Chapter
Part of the Frontiers in Electronic Testing book series (FRET, volume 21)

Abstract

The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities IEEE P1500 Standard for Embedded Core Test (SECT) is a standardunder-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of core-based system chips, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its scalable wrapper architecture, its test information transfer model described in a standardized Core Test Language, and its two compliance levels. The standard is still under development, and this paper only reflects the view of six active participants of the standardization committee on its current status.

Keywords

embedded cores standardization core test wrapper core test language compliance levels 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    S. Adham et al., “Preliminary Outline of IEEE P1500 Scalable Architecture for Testing Embedded Cores,” in Proceedings IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 1999, pp. 483–488.Google Scholar
  2. 2.
    T. Anderson, “This is Hard Core,” Test—The European Test Industry Journal, vol. 25, no. 5, pp. S5–S6, June 1999.Google Scholar
  3. 3.
    K. Chakrabarty, “Test Scheduling for Core-Based Systems,” in Proceedings International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 1999, pp. 391–394.Google Scholar
  4. 4.
    K. Chakrabarty, “Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming,” IEEE Transactions on Computer-Aided Design, vol. 19, no. 10, pp. 1163–1174, Oct. 2000.CrossRefGoogle Scholar
  5. 5.
    R.K. Gupta and Y. Zorian, “Introducing Core-Based System Design,” IEEE Design and Test of Computers, vol. 14, no. 4, pp. 15–25, Dec. 1997.CrossRefGoogle Scholar
  6. 6.
    IEEE 1450 Web Site. http://grouper.ieee.org/groups/1450/.Google Scholar
  7. 7.
    IEEE Computer Society, IEEE Standard Test Interface Lan-guage (STIL) for Digital Test Vector Data—Language Manual—IEEE Std. 1450.0–1999. New York: IEEE, Sept. 1999.Google Scholar
  8. 8.
    IEEE Computer Society, IEEE Standard Test Access Port and Boundary-Scan Architecture—IEEE Std. 1149.1–2001. New York: IEEE, July 2001.Google Scholar
  9. 9.
    V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores,” Journal of Electronic Testing: Theory and Applications, vol. 18, no. 2, pp. 213–230, April 2002.CrossRefGoogle Scholar
  10. 10.
    R. Kapur et al., “P1500-CTL: Towards a Standard Core Test Language,” in Proceedings IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 1999, pp. 489–490.Google Scholar
  11. 11.
    R. Kapur et al., “CU—The Language for Describing Core-Based Test,” in Proceedings IEEE International Test Conference (ITC), Baltimore, MD, Oct. 2001, pp. 131–139.Google Scholar
  12. 12.
    M. Keating and R. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Norwell, Massachusetts: Kluwer Academic Publishers, June 1999.Google Scholar
  13. 13.
    E. Larsson and Z. Peng, “An Integrated System-on-Chip Test Framework,” in Proceedings Design, Automation, and Test in Europe (DATE), Munich, Germany, March 2001, pp. 138144.Google Scholar
  14. 14.
    E. Larsson and Z. Peng, “Test Scheduling and Scan-Chain Division Under Power Constraint,” in Proceedings IEEE Asian Test Symposium (ATS), Kyoto, Japan, Nov. 2001, pp. 259–264.Google Scholar
  15. 15.
    Manufacturing-Test Related DWG. Test Data Interchange Formats and Guidelines for VC Providers. VSI Alliance, Los Gatos, CA, Jan. 2001.Google Scholar
  16. 16.
    E.J. Marinissen, “The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs,” Journal of Electronic Testing: Theory and Applications, vol. 18, no. 4, pp. 435–454, Aug. 2002.CrossRefGoogle Scholar
  17. 17.
    E.J. Marinissen, S.K. Goel, and M. Lousberg, “Wrapper Design for Embedded Core Test,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Oct. 2000, pp. 911920.Google Scholar
  18. 18.
    E.J. Marinissen and Y. Zorian, “Challenges in Testing Core-Based System ICs,” IEEE Communications Magazine, vol. 37, no. 6, pp. 104–109, June 1999.CrossRefGoogle Scholar
  19. 19.
    E.J. Marinissen, Y. Zorian, R. Kapur, T. Taylor, and L. Whetsel, “Towards a Standard for Embedded Core Test: An Example,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Sept. 1999, pp. 616–627.Google Scholar
  20. 20.
    M. Sugihara, H. Date, and H. Yasuura, “A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 465–472.Google Scholar
  21. 21.
    T. Taylor and G. Maston, “Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Nov. 1996. IEEE Computer Society Press, pp. 565–570.Google Scholar
  22. 22.
    J. van Beers and H. van Herten, “Test Features of a Core-Based Co-Processor Array for Video Applications,” in Proceedings IEEE International Test Conference (ITC), Atlantic City, NJ, Sept. 1999, pp. 638–647.Google Scholar
  23. 23.
    P. Vanna and S. Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 294–302.Google Scholar
  24. 24.
    VSI Alliance Web Site. http://www.vsi.org/.Google Scholar
  25. 25.
    L. Whetsel and M. Ricchetti, “Tapping into IEEE P1500 Domains,” in Digest of Papers of IEEE International Workshop on Testing Embedded Core–Based Systems (TECS), Marina del Rey, CA, May 2001, pp. 3.2–1–7.Google Scholar
  26. 26.
    Y. Zorian, “Test Requirements for Embedded Core-Based Systems and IEEE P 1500,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Nov. 1997, pp. 191–199.Google Scholar
  27. 27.
    Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” in Proceedings IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 130143.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Erik Jan Marinissen
    • 1
  • Rohit Kapur
    • 2
  • Maurice Lousberg
    • 1
  • Teresa McLaurin
    • 3
  • Mike Ricchetti
    • 4
  • Yervant Zorian
    • 5
  • Krishnendu Chakrabarty
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands
  2. 2.Synopsys, Inc.SunnyvaleUSA
  3. 3.ARM, Inc.AustinUSA
  4. 4.Intellitech Corp.DurhamUSA
  5. 5.LogicVision, Inc.San JoseUSA

Personalised recommendations