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Analysis and Measurement of Crosstalk-Induced Delay Errors in Integrated Circuits

  • F. Moll
  • M. Roca
  • A. Rubio
  • E. Sicard

Abstract

Measurements are presented of the effect that line coupling produces on the transition delay of a signal when a signal commutes simultaneously in an adjacent line. A specific test circuit for the measurements has been used, implemented with an ASIC in 1.2 µm technology.

Keywords

Clock Period Spurious Signal Coupling Capacitance Transition Delay Delay Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    MoIl F. and Rubio A., Spurious Signals in Digital CMOS VLSI Circuits A propagation Analysis”, IEEE Transactions on Circuits and Systems-fl, 39(10). 1992.Google Scholar
  2. 2.
    Brews MA. and Gupta S.K., Process Aggravated Noise (PAN) New Validation and Test Problems”, IEEE International Test Conference, 1996.Google Scholar
  3. 3.
    linger S,H. and Tan Cl., “Clocking Schemes for High-Speed Digital Systems”, IEEE Transactions on Computers, C-35(lO), October 1986.Google Scholar

Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • F. Moll
    • 1
  • M. Roca
    • 2
  • A. Rubio
    • 1
  • E. Sicard
    • 3
  1. 1.Departament d’Enginyeria ElectrònicaUPCBarcelonaSpain
  2. 2.Departament de FísicaUIBIlles BalearsSpain
  3. 3.Département de Génie Electrique et InformatiqueINSAToulouseFrance

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