Abstract
A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz-100 kHz, and it has a power dissipation of 254 nW/ pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-µm mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm2 without the i/o pads
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El-Masry, E.I., Wu, J. (2000). Low Voltage Micropower Log-Domain Filters. In: Serdijn, W.A., Mulder, J. (eds) Research Perspectives on Dynamic Translinear and Log-Domain Circuits. The Springer International Series in Engineering and Computer Science, vol 550. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6414-7_8
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DOI: https://doi.org/10.1007/978-1-4757-6414-7_8
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